Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMULL2 (vector, 4S)

Test 1: uops

Code:

  smull2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)093f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230082254825100010001000398313030180303730372415328951000100020003037303711100110008073116112630100030383038303830383038
10043037220061254825100010001000398313030180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313130180303730372415328951000100020003037303711100110000373116112630100030383038303830383038
100430372300198254825100010001000398313130180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313030180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313130180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313130180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313130180303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018030373037241532895100010002000303730371110011000010273116112630100030383038303830383038
10043037220061254825100010001000398313030180303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  smull2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000011410000577427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500842954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954845101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000066402162229630010000103003830038300383003830038
1002430037224000612954825100101010000101000050427731303001830037300372828773287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  smull2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240072629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225008429548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002042000030037300371110201100991001001000010012237101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728268328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548641010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383018130038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250012229548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250044129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300841110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001910100081010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250014929548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250010529548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250056329548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  smull2 v0.4s, v8.8h, v9.8h
  smull2 v1.4s, v8.8h, v9.8h
  smull2 v2.4s, v8.8h, v9.8h
  smull2 v3.4s, v8.8h, v9.8h
  smull2 v4.4s, v8.8h, v9.8h
  smull2 v5.4s, v8.8h, v9.8h
  smull2 v6.4s, v8.8h, v9.8h
  smull2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915001252580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511041611200360800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611201990800001002004020040200402004020040
802042003915004212580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500622580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080102200160000200982009821802011009910010080000100045100005110250112003625800001002009320092200922004020040
8020420039150041258010010080000100800005006400001200282003920039997339997801002008000020016000020039200392180201100991001008000010002526000511011611200360800001002004020040200402004020040
802042003915012412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915003262580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000001032580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200001516201662003600080000102004020040200402004020040
800242003915000001032580010108000010800005064000001200432003920039999631001980010208000020160000200392003911800211091010800001000050200006160015152003600080000102004020040200402004020040
80024200391500000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200006160015152003600080000102004020040200402004020040
80024200391500000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200006160015152003600080000102004020040200402004020040
800242003915000001057258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100005020000516001662003600080000102004020040200402004020040
8002420039150000040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100005020000616001662003620080000102004020040200402004020040
800242003915000001282580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200001616105152003600080000102004020040200402004020040
80024200391500000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200005160015152003600080000102004020040200402004020040
800242003915000002122580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200001616006162003600080000102004020040200402004020040
80024200391500000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050200001616005152003600080000102004020040200402004020040