Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMULL (vector, 8H)

Test 1: uops

Code:

  smull v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230103625482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  smull v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000536295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830083
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000607101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000607101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000607101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630110000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006692162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372252101086129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000101006402162229630010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000101006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001410000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  smull v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100035015071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000390371011611296340100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000370071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000420071011611296340100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000310371011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000420071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000330071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000380277371011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000001571011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000340071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001053900640216222963010000103003830038300383003830038
10024300372250536295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010471122300640216222963010000103003830038300383008530038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001036000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001051500640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001011000640216222963010000103003830038300383003830038
1002430037225072629548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001042300640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001043843600640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001037000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001038000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001027300640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  smull v0.8h, v8.8b, v9.8b
  smull v1.8h, v8.8b, v9.8b
  smull v2.8h, v8.8b, v9.8b
  smull v3.8h, v8.8b, v9.8b
  smull v4.8h, v8.8b, v9.8b
  smull v5.8h, v8.8b, v9.8b
  smull v6.8h, v8.8b, v9.8b
  smull v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511021611200360800001002004020040200402004020040
802042003915000001272580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
8020420039150001202522580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
802042003915000002632580305100800001008000050064000020020200392003999733999780100200800002001600002003920091118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391510000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000010511011611200360800001002004020040200402004020040
80204200391500400412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200800800001002004020040200402004020040
80204200391500000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011613200360800001002004020040200402004020040
802042003915000001062580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000310511011611200360800001002014720040200402004020040
802042003915000006592580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020040200402004020040
80204200391500000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000511011611200360800001002004020145200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000010725800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020216112003680000102004020040200402004020040
800242003915000006125800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020416212003680000102004020040200402004020040
80024200391500000862258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000036035020116112003680000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000049065020116112003680000102004020040200402004020040
800242003915000006125800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020116112003680000102004020040200402004020040
8002420039150000067525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000005020116112003680000102004020040200402004020040
8002420039150000020825800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000005020416432003680000102004020040200402004020040
8002420039150000012425800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000005020116112003680000102004020040200402004020040
8002420039150000027525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100001205020116112003680000102004020040200402004020040
800242003915000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000005020116112003680000102004020040200402004020040