Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQABS (scalar, B)

Test 1: uops

Code:

  sqabs b0, b0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300000006125472510001000100039816003018303730372414328951000100010003037303711100110000000000073216112629100030383038303830383038
100430372300000006125472510001000100039816003018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
1004303722000078006125472510001000100039816013018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
100430372200000006125472510001000100039816003018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
100430372200000006125472510001000100039816003018303730372414328951000100010003037303721100110000000000073116112629100030383038303830383038
100430372200000006125472510001000100039816003018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
1004303723000012006125472510001000100039816013018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
1004303723000000061254725100010001000398160030183037303724143289510001000100030373037111001100000000048073116112629100030383038303830383038
100430372300000006125472510001000100039816003018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
100430372300000006125472510001000100039816013018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqabs b0, b0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000870612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018302303003728264328745101002001000020010000300373003711102011009910010010000100200000071011611296330100001003003830038300383003830038
1020430037224000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000030071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100003000071011611296330100001003003830038300383003830038
10204300372250000007032954725101001001000010010000500427716030018300373022728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000030071011611296330100001003003830038300383003830038
10204300372250000210612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038
1020430037225000000612954725101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250084061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640516552962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640516562962910000103003830081300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640616662962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640616562962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640516552962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300842828632876710010201000020100003003730037111002110910101000010000640516562962910000103003830038300383003830038
10024300372250027061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640616642962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640616652962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000640616652962910000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010330640616652962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqabs b0, b8
  sqabs b1, b8
  sqabs b2, b8
  sqabs b3, b8
  sqabs b4, b8
  sqabs b5, b8
  sqabs b6, b8
  sqabs b7, b8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611500302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118216020036800001002004020040200402004020040
802042003915003152580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020114
80204201011500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040
80204200391500722580108100800081008002050064013202002020039200399977699908022220080032200801392003920039118020110099100100800001002131115118016120036800001002009920143200402004020040
80204200391500302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040
80204200391500722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000031115118016020036800001002004020040200402004020040
802042003915012302580108100800081008002050064013202002020039200939977699908012020080032200800322003920039118020110099100100800001000001115155016020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000012004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000000050205164220036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000000050204164220036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080213200392003911800211091010800001000000000050204164420036080000102004020040200402004020040
8002420039150000024004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000000050204164220036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020022200392003999963100198001020800002080000200392003911800211091010800001000000000050204164420036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000010000050203162420036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000000050204164220036080000102004020040200402004020040
800242003915000009004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000010000050204163420036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000000050204162420036080000102004020040200402004020040
800242003915000000004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000000050204164420036080000102004020040200402004020040