Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQABS (vector, 2S)

Test 1: uops

Code:

  sqabs v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100030275373116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372266125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372206125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372306125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723012425472510001000100039816030183037303724143289510001000100030373037111001100001073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqabs v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003008530038300383003830038
1020430037224061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000008429547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000008229547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000102000006402162229629010000103003830038300383003830038
100243003722400000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqabs v0.2s, v8.2s
  sqabs v1.2s, v8.2s
  sqabs v2.2s, v8.2s
  sqabs v3.2s, v8.2s
  sqabs v4.2s, v8.2s
  sqabs v5.2s, v8.2s
  sqabs v6.2s, v8.2s
  sqabs v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150009030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003931802011009910010080000100000011151180160020036800001002004020040200402004020040
80204200391500000108258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080084100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000074258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd0d2d5map dispatch bubble (d6)dbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200051606720036080000102004020040200402004020040
800242003915000041825800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200061606420036080000102004020040200402004020040
80024200391500006125800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001009050200041604320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200041606720036080000102004020040200402004020040
800242003915000010325800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200071606620036080000102004020040200402004020040
800242003915000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010183050200031606420036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200061606620036080000102004020040200402004020040
800242003915000010525800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000150200041603420036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000050200061604320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020070200392003999963100198001020800002080000200392003921800211091010800001000050200031603420036080000102010220040200402004020040