Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQADD (scalar, B)

Test 1: uops

Code:

  sqadd b0, b0, b1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723756125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100002073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372308425482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722010325482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372408225482510001000100039831330183037303724153289510001000200030373037111001100000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqadd b0, b0, b1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250001072954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722503930612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225030612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722503120612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383008130038
10204300372250300612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722503030612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250210912954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250988612954825101001001000010010000500427731313001830037300372826532874510100200101662002000030084300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225005880612954825100101010000101000050427731330018300373003728287328767101622010000202000030037300371110021109101010000100000006406162229630010000103003830038300383003830038
10024300372240000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731330018300373003728287328767100102010000222000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722400001242954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000016402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037301321110021109101010000100013207033242229630210000103013330132300383003830038
100243017922501088612954825100101010008101000050427731330018300373003728287328767100102010163202000030037300371110021109101010000100009006402242229630010000103003830038300383003830038
1002430037225001320612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000102010006402162229630210000103008430038300853023030276
1002430037225004501032954825100101110000101000050427731330018300853003728287328767100102010161222032430037300371110021109101010000100010406402242229630010000103003830038300383008530038

Test 3: Latency 1->3

Code:

  sqadd b0, b1, b0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372254206129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722556106129548251010010010000100100005004278633300543003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372253306129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372251206129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372251806129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225606129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372251560612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100001357101161130034100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722515906129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722510206129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000900612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000000006403163329630010000103003830038300383003830038
100243003722500000246007262954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000000007044653329630010000103003830038300383003830038
1002430037225000002400612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000000006403163329630010000103003830038300383003830038
10024300372250000024900612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000000006403163329630010000103003830038300383003830038
100243003722500000252002322954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000000006403163329630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731330018300373003728287328767100102010000202000030037300841110021109101010000100001000006403163329630010000103003830038300383003830038
10024300372250000024006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000123300007263164529630010000103003830038300383003830038
100243003722500100264006129548251001010100001010000504277313301263003730037282873287671001020103252020658301813017951100211091010100001000010186250006614904329906210000103040730086303653041530416
100243008523010164948616051502948512210070191005617110439942854553027030372304132831335288991090724109982222298303683036791100211091010100001020010169932007873333329882310000103036930372301333036830371
100243036922600187936616052292947615910071151005613110436642868123030630413303652829533289151105922114792422948304523041951100211091010100001002204250580008084824329953510000103041830417304663045230417

Test 4: throughput

Count: 8

Code:

  sqadd b0, b8, b9
  sqadd b1, b8, b9
  sqadd b2, b8, b9
  sqadd b3, b8, b9
  sqadd b4, b8, b9
  sqadd b5, b8, b9
  sqadd b6, b8, b9
  sqadd b7, b8, b9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500000540041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000000511021611200360800001002004020040200402004020040
8020420039150000034500832580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000003000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000012002020039200399973229997801002008000020016063220039200391180201100991001008000010000010000511011611200770800001002004020040200402004020040
802042003915000005100562580100100800001008000050064000012002020112200399990399978010020080000200160000200392003911802011009910010080000100000003005228174112015623800001002030320347202962029420297
802042035115211779545280130015580806122806791148083461164574412030620394204051003838101858085720080733200161254204132039981802011009910010080000100200023340005245194112032920800001002024720040200402004020040
802042003915000002401112344808071218068612080728620641640120306204042040610047301021180855200807312021614362044720139818020110099100100800001000001033182051451104112039823800001002044720460204632045820508
8020420517153009914048804125802101008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000201233104052291118112036323800001002046220455204562050720194
80204205031530175130870401498176810031258068212080314603647316120145205182046610045391020880957200808302001618882047220197918020110099100100800001000000060052271125112036619800001002045620504204512045420504
80204204671531000675616041258010010080000100800005006400001200202009920039997339997801002008000020016000020039200391180201100991001008000010000000283500511011611200360800001002004020040200402004020040
80204200391510155124401113816980417127813621218112863964885012057920655208149973601040181667202815652041600002003920039118020110099100100800001000000023450052462180112064120800001002061520610205612051320871

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000090400258040510800001080000506400000120020200392003999963100198001020800002016000020141200391180021109101080000100020000502031602320036080000102004020040200402004020040
8002420039150000270400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031603220036080000102004020040200402004020040
800242003915000000400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031603320036080000102004020040200402004020040
800242003915000090400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031602320036080000102004020040200402004020040
8002420039150000480400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031602320036080000102004020040200402004020040
8002420039150000330400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031603320036080000102004020040200402004020040
800242003915000000400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502021603220036080000102004020040200402004020040
80024200391500005370400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100001194500502031603320036080000102004020040200402004020040
80024200391500001200400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031603320036080000102004020040200402004020040
8002420039150000930400258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502031603320036080000102004020040200402004020040