Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQADD (scalar, D)

Test 1: uops

Code:

  sqadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723015625482510001000100039831303018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037231525125482510001000100039831313018303730372415328951000100020003037303711100110000973116112630100030383038303830383038
100430372306125482510001000114939831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
1004303723029525482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300372110201100991001001000010000071021611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402242229630010000103003830038300383003830038
10024301322250361295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqadd d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018300373003728265328745101002001000020020662300373003711102011009910010010000100000710216222963416100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722530612954825101001001000010010000500427731313001830037300372826532874510100200100002002131830037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000171021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006403162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006404162229630210000103003830086300863003830038
1002430037225110130295302510021121000014101495042773130300183003730037282873287671001020100002020000300373008111100211091010100001001006403162229630010000103003830038300383003830038
1002430037225001261295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006404162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001001006404162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373018111100211091010100001000006404162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300543003730085282873287671001020100002020000300373003711100211091010100001000006403162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006404162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqadd d0, d8, d9
  sqadd d1, d8, d9
  sqadd d2, d8, d9
  sqadd d3, d8, d9
  sqadd d4, d8, d9
  sqadd d5, d8, d9
  sqadd d6, d8, d9
  sqadd d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051103161120036800001002004020040200402004020040
8020420039150051625801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915064125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001002051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200902004020040
8020420039150031725801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020095

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000940258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000104000050200101610820036080000102004020040200402004020040
800242003915000069747258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000100200050200816101020036080000102004020040200402004020040
80024200391500000402580010108009910800005064000000200202003920039999631001980010208000020160000200892009211800211091010800001000000502009168920036080000102004020040200402004020040
8002420039150000366402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000000502009167820036080000102004020040200402004020040
80024200391500000402580010108000010800975064000001200202003920039999631001980010208000020160000200392003911800211091010800001000000502006167920036080000102004020040200402004020040
80024200391500006402580010108000010800005064000001200202003920039999631001980123208000020160000200392003911800211091010800001000200502009168620036080000102004020040200402004020040
80024200391500016612580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000000502008166920036080000102004020040200402004020040
800242003915000036822580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000100502008167820036080000102004020040200402004020040
8002420039150000453402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000006502006167820036080000102004020040200402004020040
800242003915000005152580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000000502009166920036080000102004020040200402004020040