Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQADD (vector, 4S)

Test 1: uops

Code:

  sqadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372300198012125482510001000100039831313018303730372415328951000100020003037303711100110000073116112823100030383038303830383038
10043037230023406125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000010325482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372300006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372200006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372300006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723003906125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722001206125482510001000100039831313018303730372415328951000100020003037303711100110000973116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225012629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722506129539451010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372254512629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225014529548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225014729548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100210007101161129634100001003003830038300383003830038
102043003722506129530251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500084295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000346295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225100835295482510010101000010100005042773131300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225100105295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006422162229630210000103003830038300383003830038
100243003722500061295482510010101000010100006042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000168295482510020101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000191295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630210000103003830038300383003830038
1002430037225000229295482510010101000010100005042773130300183300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002530037225000342295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqadd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500011242954825101001001000010010000500427731303001830037300372826532874510100200100002002000030084300371110201100991001001000010000071051725296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500150612954825101001001000010010000626427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240000612954825101251251000012510000626427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071451715296340100001003003830038300383003830038
10204300372250001612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240001612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500001452954825101251251000012510000626427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200101762002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722501452954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640316222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103008230038300383003830038
100243003722501032954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722401032954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722502542954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000100640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqadd v0.4s, v8.4s, v9.4s
  sqadd v1.4s, v8.4s, v9.4s
  sqadd v2.4s, v8.4s, v9.4s
  sqadd v3.4s, v8.4s, v9.4s
  sqadd v4.4s, v8.4s, v9.4s
  sqadd v5.4s, v8.4s, v9.4s
  sqadd v6.4s, v8.4s, v9.4s
  sqadd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039150083258010010080000100800005006400000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051102161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150062258010010080000100800005006400001200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150062258010010080000100800005006400000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
80204200391500421258010010080000100800005006400001200203200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200200200392003999730399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000174258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000216001120036080000102004020040200402004020040
80024200391500040258001012800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
800242003915000210258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020197200402004020040
8002420039150088126258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116003120036080000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
80024200391501040258001010800001080000506400000200202003920039999631001980012208000020160000200392003911800211091010800001005020000116001120036080000102004020040200402004020040
80024200391500082258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005020000116003220036080000102004020040200402004020040