Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQADD (vector, 8B)

Test 1: uops

Code:

  sqadd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
10043037220612548251000100010003983130301830373037241532895100010002000303730371110011000173216222630100030383038303830383038
10043037230842548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
10043037230822548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
1004303723121562548251000100010003983130301830373037241572895100010002000303730371110011000073216222630100030383038303830383038
10043037220612548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038
100430372212612548251000100010003983130301830373037241532895100010002000303730371110011000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqadd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240044510329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500006129548251010010010000100101495004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225000094329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225000010329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010001567101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000000612954825100101010000101000050427731303001803003730084282870328767100102010000202000030037300371110021109101010000100000006403162229630010000103003830038300383003830038
10024300372240000000612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427846903001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001833003730037282870328767100102010000202000030037300371110021109101010000100000006402483529774110000103027230273302743027530086
10024300852251000000612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100010306402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830061300383003830038
10024300372250000000612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqadd v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000003071011611296340100001003003830038300383003830038
1020430037224000006129548251010010010000100100005004277313130018030037300372826532874510100200100002002000030037300371110201100991001001000010000000129071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000001740710116112963415100001003003830038301313003830038
1020430037225002413261295398310154100100001291000054742773131300900302733021628265142878110731204106662282231830466303717110201100991001001000010024214269450776116212975725100001003003830185302773008530085
1020430037225105107792954825101241271000010010298500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000000000710116112963420100001003003830038300383003830038
1020430037225010133128295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000003071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000006071011611296340100001003003830038300383003830038
10204301312250000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000003071011611296340100001003003830038300383003830038
10204300372250000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000003071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001010000640616332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372260061295486210010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001003000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100141000640316332963010000103003830038300383003830038
100243003722500612954825100191010000101000050427731330018300373003728287032876710010201000020200003003730037111002110910101000010656000640316332963010000103003830038300383003830038
100243003722500536295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024301302250061295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
100243003722500726295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372240053629548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100168000640316332963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqadd v0.8b, v8.8b, v9.8b
  sqadd v1.8b, v8.8b, v9.8b
  sqadd v2.8b, v8.8b, v9.8b
  sqadd v3.8b, v8.8b, v9.8b
  sqadd v4.8b, v8.8b, v9.8b
  sqadd v5.8b, v8.8b, v9.8b
  sqadd v6.8b, v8.8b, v9.8b
  sqadd v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815000085258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000600511041611200360800001002004020040200402004020040
8020420039150101044125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000012900511011611200360800001002004020040200402004020040
80204200391500007025801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000381800511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010001813200511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100022000511011611200360800001002004020040200402004020040
80204200391501006225801001008000010780000500640000120020200992009199733999780100200800002001600002003920093118020110099100100800001002181205110116112003615800001002009920040200402004020040
80204200391500004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000111100511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010002300511011611200360800001002004020040200402004020040
8020420039150012041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000900511011611200360800001002004020040200402004020040
8020420039150000412580100100800001008000050064000002002020039200399973399978010020080208200160000200392025011802011009910010080000100017300511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000502021664200360080000102004020040200402004020040
800242003915000004025800101080000108000050640000112002020039200399996310019800102080000201600002003920039118002110910108000010493502021644200360080000102004020040200402004020040
8002420039150000040258001010800001080000506400000120020200392003999963100198001020800002016000020039200391180021109101080000103415502021624200360080000102004020040200402004020040
80024200391500000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000502041644200360080000102004020040200402004020040
800242003915000004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010490502021624200360080000102004020040200402004020040
80024200391500000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000502041624200360080000102004020040200402004020040
800242003915000006125800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010293502041624200360080000102004020040200402004020040
80024200391500000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001003502041624200360080000102004020040200402004020040
80024200391500000402580012108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502041624200360080000102004020040200402004020040
800242003915000004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010156502041636200360080000102004020040200402004020040