Firestorm: SQDMLAL2 (by element, 2D) measurements

Code:

  sqdmlal2 v0.2d, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	589	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	105	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	686	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	170	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqdmlal2 v0.2d, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10166	200	31488	30133	30037	1	1	10201	100	99	100	100	10000	100	4	3	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	29635	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	985	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	3	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	84	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	108	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqdmlal2 v0.2d, v0.4s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	204	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	3	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	170	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	1	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10158	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqdmlal2 v0.2d, v1.4s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	61	29548	45	10100	100	10000	100	10000	644	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30492	30037	30037	1	1	10201	100	99	100	100	10000	100	1	3	0	0	710	1	16	1	2	29634	11	10000	100	30038	30133	30038	30038	30038
10204	30037	225	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	3	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	44	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	710	1	16	1	1	29670	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	12	108	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	12	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30498	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	850	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	4	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	4	11	16	12	7	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	4	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	642	4	11	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	4	30018	30081	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	642	3	11	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	738	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	3	11	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	3	11	16	12	12	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	8361	0	644	3	11	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30084	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	3	11	16	12	11	29630	0	10000	10	30038	30038	30038	30038	30225
10024	30037	224	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	3	11	16	11	6	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	68	29548	25	10010	10	10000	10	10596	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	2	644	3	11	16	6	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	0	0	0	0	2	733	29548	25	10010	10	10000	10	10000	50	4277313	1	3	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	3	11	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlal2 v0.2d, v8.4s, v9.s[1]
  movi v1.16b, 0
  sqdmlal2 v1.2d, v8.4s, v9.s[1]
  movi v2.16b, 0
  sqdmlal2 v2.2d, v8.4s, v9.s[1]
  movi v3.16b, 0
  sqdmlal2 v3.2d, v8.4s, v9.s[1]
  movi v4.16b, 0
  sqdmlal2 v4.2d, v8.4s, v9.s[1]
  movi v5.16b, 0
  sqdmlal2 v5.2d, v8.4s, v9.s[1]
  movi v6.16b, 0
  sqdmlal2 v6.2d, v8.4s, v9.s[1]
  movi v7.16b, 0
  sqdmlal2 v7.2d, v8.4s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	151	0	39	25	80100	100	80000	100	80000	500	640000	20110	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	229	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	1	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	375	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	3	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20062	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	0	20031	20050	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10030	3	1	1	12	20	2	1	1	10	7	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	171	0	615	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	6	2	2	8	24	4	2	2	10	7	20047	2	30	0	160000	10	20051	20051	20051	20051	20051
160024	20050	151	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	2	1	7	20	2	1	1	10	10	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10036	6	2	2	10	24	4	2	2	10	8	20047	2	30	0	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20031	20050	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10036	6	2	2	10	24	4	2	2	7	10	20047	2	30	0	160000	10	20051	20051	20051	20051	20051
160024	20046	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	1	2	10	24	2	2	1	10	7	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20050	150	0	0	0	0	0	108	25	80012	12	80000	12	80000	62	640000	1	1	20031	20046	20046	3	22	80012	20	80000	20	240000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	2	1	10	20	2	1	1	10	7	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20050	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20050	20046	3	22	80117	20	80208	20	240000	20046	20289	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	1	1	10	20	2	1	1	10	8	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	1	1	10	20	2	1	1	10	7	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	151	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10030	3	1	1	10	20	2	1	1	7	10	20043	2	15	0	160000	10	20047	20047	20047	20047	20047

Test 6: throughput

Count: 12

Code:

  sqdmlal2 v0.2d, v12.4s, v13.s[1]
  sqdmlal2 v1.2d, v12.4s, v13.s[1]
  sqdmlal2 v2.2d, v12.4s, v13.s[1]
  sqdmlal2 v3.2d, v12.4s, v13.s[1]
  sqdmlal2 v4.2d, v12.4s, v13.s[1]
  sqdmlal2 v5.2d, v12.4s, v13.s[1]
  sqdmlal2 v6.2d, v12.4s, v13.s[1]
  sqdmlal2 v7.2d, v12.4s, v13.s[1]
  sqdmlal2 v8.2d, v12.4s, v13.s[1]
  sqdmlal2 v9.2d, v12.4s, v13.s[1]
  sqdmlal2 v10.2d, v12.4s, v13.s[1]
  sqdmlal2 v11.2d, v12.4s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30113	230	0	1	0	30	0	53	1497	0	25	120101	100	120000	100	120000	500	960000	0	30023	30039	30039	14973	3	14997	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	2	16	1	1	30039	0	120000	100	30944	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	41	0	25	120101	100	120000	100	120000	500	4289539	0	30020	30943	30039	14973	3	15901	120100	200	120000	200	360000	30943	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	30040	30043	30040	30040	30041
120204	30039	225	0	0	0	0	0	53	41	0	25	120117	100	120000	100	120000	500	960000	0	30021	30039	30039	14973	3	15901	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	1	0	0	7610	1	16	1	1	30940	0	120000	100	30923	30040	30040	30040	30040
120204	30039	231	0	0	0	0	0	0	41	0	25	120100	100	120001	100	120000	500	960000	0	30023	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	31738	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	30043	30040	30040	30043	30040
120204	30943	225	0	0	0	0	0	0	41	3405	25	120100	100	120034	100	120000	500	960000	0	30020	30039	30922	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	2	0	0	7610	1	16	1	1	30940	0	120000	100	30043	30040	30040	30040	30040
120204	30039	231	0	0	0	0	0	0	44	0	25	120100	100	120001	100	120000	500	960000	1	30020	30943	30039	14973	3	15000	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	30043	30040	30040	30040	30040
120205	30039	225	0	0	0	0	0	0	41	0	25	120100	100	120000	100	120000	500	960000	1	30924	30039	30039	14973	3	14997	120100	200	120000	200	360000	30922	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30940	0	120000	100	30040	30944	30040	30040	30040
120204	30039	225	0	0	0	0	0	1	41	0	25	120101	100	120000	100	120000	500	4283400	0	30020	30042	30039	15828	3	14997	120100	200	120000	200	360000	30039	30042	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31750	30040	30923	30040	30040
120204	30039	232	0	0	0	0	0	0	61	0	25	120101	100	120000	100	120000	500	990000	0	30020	30042	30039	14973	3	15000	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	30040	30040	30043	30040	30944
120204	30039	225	0	0	0	0	0	0	61	0	25	120101	114	120000	100	120000	500	960000	0	30020	30039	30039	14973	3	15880	120100	200	120000	200	360000	30039	30922	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31254	30096	30040	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30050	225	0	0	0	0	0	0	12	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	0	1	5	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	16	0	93	7525	11	6	2	34	16	3	2	2	27	28	30036	0	31	17	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	0	58	0	25	120010	10	120000	12	120000	50	1130356	0	1	5	30021	30039	30039	14996	8	15990	120434	20	120000	20	360660	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	4	2	0	7550	11	6	2	27	16	3	2	2	28	28	30036	0	31	10	120000	10	30040	30040	30043	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	1	52	0	25	120010	10	120000	10	120000	50	960000	0	1	5	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	25	0	9	7524	11	6	2	16	16	3	2	2	26	26	30036	0	31	10	120000	10	30040	30040	30041	30040	30040
120024	30039	225	0	0	0	0	0	0	6	0	0	1	58	0	25	120010	10	120000	10	120000	50	960000	0	1	5	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	29	0	15	7525	11	5	2	28	16	3	2	2	27	26	30036	0	31	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	0	52	3405	25	120010	10	120000	10	120000	50	960000	0	1	5	30021	30039	30922	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	7	0	3	7524	11	6	2	14	16	3	2	2	27	12	30036	0	31	10	120000	10	30040	30040	30043	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	1	52	0	25	120010	10	120000	10	120000	50	960000	0	1	10	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7524	16	7	2	23	16	3	2	2	28	28	30036	0	31	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	0	1	10	30020	30922	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	4	0	483	7525	16	6	2	26	16	3	2	2	26	27	30036	0	31	10	120000	10	30040	30040	30040	31011	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	0	58	0	25	120010	10	120000	10	120000	50	960000	0	1	10	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	1	0	0	7524	16	7	2	28	16	3	2	2	29	30	30036	0	31	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	0	58	0	25	120010	10	120000	10	120000	50	960000	0	1	10	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	1	0	0	7525	16	7	2	27	16	3	2	2	16	28	30036	0	31	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	1	58	0	25	120010	10	120000	10	120000	50	960000	0	1	10	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	1	0	0	7524	16	7	2	27	16	3	2	2	27	22	30036	0	31	10	120000	10	30040	30040	30042	30040	30040

SQDMLAL2 (by element, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations