Firestorm: SQDMLAL (vector, 4S) measurements

Code:

  sqdmlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	9	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	7	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	6	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqdmlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	44	0	3	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	61	29548	25	10100	102	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	712	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	0	3	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30133	30038	30038
10204	30037	225	0	0	0	33	0	1	145	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28269	3	28745	10100	204	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	10	2	0	710	1	3	16	3	3	29706	0	10000	100	30038	30038	30038	30038	30038
10204	30037	227	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	0	12	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	6	0	0	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	35	0	3	712	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	3	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	3	16	3	3	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	28	3	0	640	4	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	33	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	51	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	40	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	226	1	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30084	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	35	3	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	13	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	36	0	0	640	4	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	15	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	42	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqdmlal v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	84	29548	25	10100	124	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30181
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	3	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	1	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	1	0	1	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30084	224	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	3	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	56	0	6	0	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	358	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	61	0	3	0	0	640	3	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	60	0	6	0	0	640	2	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	506	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	0	640	3	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	41	0	6	0	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	4	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqdmlal v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	39	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28272	6	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	342	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	6	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	12	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	39	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30086	30038
10204	30037	225	0	0	27	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	6	61	29548	25	10100	100	10000	100	10000	500	4278670	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	15	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	41	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30483	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30085
10024	30084	225	0	1	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10161	20	10163	20	30000	30037	30084	2	1	10021	10	9	10	10	10000	10	4	5	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	640	2	16	2	2	29630	10000	10	30038	30171	30038	30038	30038
10024	30037	225	0	0	6	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30132	30037	28300	3	28804	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlal v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  sqdmlal v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  sqdmlal v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  sqdmlal v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  sqdmlal v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  sqdmlal v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  sqdmlal v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  sqdmlal v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	151	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	1	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	243	25	80100	100	80000	100	80000	500	640000	0	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10112	5	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640916	1	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	0	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	1	3	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	5	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	0	0	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20066	151	0	0	0	0	15	0	0	45	25	80012	12	80000	12	80000	62	640000	0	1	20027	20046	20052	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10053	3	1	1	34	20	2	1	1	29	29	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	1	2	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	0	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	6	2	1	29	26	3	2	2	18	28	20049	2	31	160000	10	20053	20053	20053	20053	20053
160024	20052	150	2	3	0	0	21	0	0	51	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10051	6	1	1	29	20	2	1	1	32	30	20043	2	15	160000	10	20053	20053	20047	20047	20047
160024	20052	150	2	2	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	1	1	20033	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	6	1	1	18	26	2	1	1	30	18	20043	2	15	160000	10	20053	20047	20047	20047	20047
160024	20046	150	2	2	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	1	1	20027	20052	20046	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10056	6	2	2	31	26	3	2	2	21	25	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20052	150	2	2	0	0	0	0	1	57	25	80012	12	80000	12	80000	62	640000	0	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10054	6	2	2	31	26	2	1	1	28	27	20043	2	15	160000	10	20053	20053	20053	20047	20053
160024	20046	150	1	1	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	1	1	20031	20046	20052	3	22	80012	20	80000	20	240000	20046	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10056	3	1	2	29	20	2	2	2	29	30	20049	2	31	160000	10	20047	20047	20047	20047	20053
160024	20052	150	1	2	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	0	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20052	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10052	6	2	2	28	20	2	1	2	19	29	20043	2	15	160000	10	20053	20047	20047	20047	20053
160024	20052	150	2	2	0	0	0	0	0	57	25	80012	12	80000	12	80000	62	640000	1	1	20027	20052	20046	3	22	80012	20	80000	20	240000	20052	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10052	6	1	2	29	20	2	2	1	32	29	20049	2	15	160000	10	20053	20047	20047	20053	20047
160024	20046	150	2	2	0	0	0	0	1	63	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10053	3	1	1	26	26	3	2	2	22	26	20049	2	15	160000	10	20053	20047	20053	20047	20047

Test 6: throughput

Count: 16

Code:

  sqdmlal v0.4s, v16.4h, v17.4h
  sqdmlal v1.4s, v16.4h, v17.4h
  sqdmlal v2.4s, v16.4h, v17.4h
  sqdmlal v3.4s, v16.4h, v17.4h
  sqdmlal v4.4s, v16.4h, v17.4h
  sqdmlal v5.4s, v16.4h, v17.4h
  sqdmlal v6.4s, v16.4h, v17.4h
  sqdmlal v7.4s, v16.4h, v17.4h
  sqdmlal v8.4s, v16.4h, v17.4h
  sqdmlal v9.4s, v16.4h, v17.4h
  sqdmlal v10.4s, v16.4h, v17.4h
  sqdmlal v11.4s, v16.4h, v17.4h
  sqdmlal v12.4s, v16.4h, v17.4h
  sqdmlal v13.4s, v16.4h, v17.4h
  sqdmlal v14.4s, v16.4h, v17.4h
  sqdmlal v15.4s, v16.4h, v17.4h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	0	0	50	25	160100	100	160017	100	160000	500	1280000	0	0	40021	40039	40039	19973	0	3	19997	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40049	40049	40040	40040	40049
160204	40039	300	0	0	0	50	25	160100	100	160017	100	160000	500	1280000	0	0	40020	40048	40039	19973	0	3	20006	160100	200	160000	200	480507	40048	40048	1	1	160201	100	99	100	100	160000	100	0	15	0	0	0	10110	2	16	2	2	40036	0	160000	100	40040	40040	40049	40049	40040
160204	40039	300	0	0	17	41	25	160100	100	160000	100	160000	500	2398999	0	0	40020	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40049	40040	40040	40049	40040
160204	40048	300	0	0	0	41	25	160100	100	160017	100	160000	500	1280000	0	0	40029	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40048	40048	1	1	160201	100	99	100	100	160000	100	44	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40100	40040	40040	40049	40040
160204	40048	300	0	0	0	41	25	160100	100	160000	100	160000	500	1280000	0	0	40020	40048	40039	19973	0	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40049	40049	40040	40040	40040
160204	40039	300	0	0	0	50	25	160117	100	160000	100	160000	500	1280000	0	0	40020	40039	40039	19973	0	3	19997	160100	200	160000	200	480000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40040	40040	40049	40049	40040
160204	40049	300	0	0	0	414	25	160100	100	160017	100	160000	500	2398999	0	0	40020	40039	40039	19973	7	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40045	0	160000	100	40049	40049	40040	40040	40040
160204	40039	300	0	0	17	41	25	160117	100	160018	100	160000	500	2398999	0	0	40029	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40049	40049	40049	40049	40040
160204	40039	300	0	0	17	50	25	160117	100	160000	100	160000	500	1280000	0	0	40029	40048	40048	19973	0	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40040	40049	40040	40040	40040
160204	40039	300	0	0	17	190	25	160100	100	160000	100	160000	500	2398999	0	0	40020	40039	40048	19973	0	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40036	0	160000	100	40049	40040	40040	40049	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	0	17	46	25	160010	10	160000	10	160000	50	1280000	2	1	40020	0	40039	40049	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	3	1	1	22	16	4	2	2	19	8	40036	0	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	1	0	0	0	0	0	0	62	25	160027	10	160000	10	160000	50	1280000	0	1	40020	0	40039	40039	19996	0	3	20029	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	16	16	4	2	2	20	20	40036	0	15	10	160000	10	40040	40040	40040	40040	40040
160024	40048	300	0	0	0	0	0	0	17	52	25	160010	10	160000	10	160000	50	2438865	0	1	40020	0	40048	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	16	16	4	2	2	10	20	40036	0	30	12	160000	10	40040	40040	40040	40040	40040
160024	40049	299	1	0	0	0	0	0	0	52	25	160027	10	160018	10	160000	50	1280000	0	1	40020	0	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	19	16	4	2	2	20	20	40036	0	30	10	160000	10	40040	40050	40040	40040	40041
160024	40048	300	0	1	1	0	0	0	0	61	25	160010	10	160000	10	160000	50	1280000	0	1	40020	0	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	19	16	4	2	2	9	20	40036	0	30	10	160000	10	40050	40050	40040	40040	40040
160024	40039	299	1	0	0	0	0	0	0	622	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	9	16	4	2	2	10	20	40036	0	30	10	160000	10	40040	40040	40040	40040	40050
160024	40039	300	1	0	0	0	0	0	0	353	25	160010	10	160000	10	160000	50	2398999	0	1	40029	0	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	9	16	4	2	2	7	19	40036	0	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40029	0	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10060	6	2	2	19	16	6	2	2	21	21	40036	0	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1320000	0	1	40020	0	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	19	16	4	2	2	19	9	40036	0	30	10	160000	10	40041	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	40020	0	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	19	16	4	2	2	10	20	40036	0	30	10	160000	10	40040	40040	40040	40040	40040

SQDMLAL (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations