Firestorm: SQDMLSL2 (by element, 2D) measurements

Code:

  sqdmlsl2 v0.2d, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	166	2548	25	1000	1000	1000	398313	1	3022	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	73	2	16	2	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	103	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	1	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	73	2	16	2	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqdmlsl2 v0.2d, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29647	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28272	6	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	30	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	6	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29647	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	12	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10148	50	4277313	0	30018	30037	30037	28287	7	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	156	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	251	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	1	0	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	536	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqdmlsl2 v0.2d, v0.4s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	4	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	9	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	96	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	189	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	6	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	87	0	716	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	44	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	68	0	3	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	5	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	3	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	4	0	6	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	57	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	0	61	29548	25	10116	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	42	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	26	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	21	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	89	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	8	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	26	11233	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	9	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	71	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	6	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28771	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	9	9	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	27	3	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	29	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	96	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30085	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	10	0	1	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqdmlsl2 v0.2d, v1.4s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	2	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	24	6	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	26	12	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	22	3	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10172	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	27	3	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	84	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	27	9	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	13	9	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	27	6	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	9	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	28	6	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	81	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30086	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl2 v0.2d, v8.4s, v9.s[1]
  movi v1.16b, 0
  sqdmlsl2 v1.2d, v8.4s, v9.s[1]
  movi v2.16b, 0
  sqdmlsl2 v2.2d, v8.4s, v9.s[1]
  movi v3.16b, 0
  sqdmlsl2 v3.2d, v8.4s, v9.s[1]
  movi v4.16b, 0
  sqdmlsl2 v4.2d, v8.4s, v9.s[1]
  movi v5.16b, 0
  sqdmlsl2 v5.2d, v8.4s, v9.s[1]
  movi v6.16b, 0
  sqdmlsl2 v6.2d, v8.4s, v9.s[1]
  movi v7.16b, 0
  sqdmlsl2 v7.2d, v8.4s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	151	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	15	10116	5	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	3	0	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	231	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	3	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	3	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	3	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	10116	1	16	1	1	2	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20052	150	0	0	0	75	25	80012	12	80000	12	80000	62	640000	1	0	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10056	11	3	2	37	26	3	2	2	18	31	20049	2	31	0	160000	10	20053	20053	20321	20071	20053
160024	20052	150	0	0	1	51	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	4	4	3	10058	6	5	2	34	26	3	2	2	33	34	20049	2	31	0	160000	10	20053	20053	20296	20070	20053
160024	20052	150	2	2	0	63	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	30	0	3	10058	11	5	2	36	26	3	2	2	32	21	20049	2	31	0	160000	10	20053	20053	20288	20070	20053
160024	20052	150	2	3	0	69	25	80012	12	80000	12	80000	62	640000	1	0	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	5	0	9	10060	11	5	2	35	26	3	2	2	34	34	20049	2	31	0	160000	10	20053	20053	20302	20070	20053
160024	20052	150	2	2	0	90	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	0	3	10059	11	5	2	17	26	3	2	2	33	34	20049	2	31	0	160000	10	20053	20053	20306	20070	20053
160024	20052	150	3	3	0	63	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	12	10061	6	5	2	34	26	3	2	2	34	35	20049	2	31	0	160000	10	20053	20053	20329	20070	20053
160024	20052	150	2	2	1	69	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	3	10042	11	5	2	19	26	3	2	2	31	33	20049	2	31	0	160000	10	20053	20053	20302	20070	20053
160024	20052	150	3	3	1	63	25	80012	12	80000	12	80000	62	640000	0	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	35	0	9	10044	11	5	2	18	26	3	2	2	33	35	20049	2	31	25	160000	10	20053	20053	20308	20070	20053
160024	20052	151	2	3	0	75	25	80012	12	80000	12	80000	62	640000	0	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	0	9	10056	8	4	1	32	20	2	1	1	18	34	20043	2	15	0	160000	10	20047	20047	20296	20069	20053
160024	20053	150	2	2	1	63	25	80012	12	80000	12	80000	62	640000	1	5	20033	20052	20052	3	22	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	0	9	10058	6	5	2	33	26	3	2	2	32	31	20049	2	31	0	160000	10	20053	20053	20300	20069	20053

Test 6: throughput

Count: 12

Code:

  sqdmlsl2 v0.2d, v12.4s, v13.s[1]
  sqdmlsl2 v1.2d, v12.4s, v13.s[1]
  sqdmlsl2 v2.2d, v12.4s, v13.s[1]
  sqdmlsl2 v3.2d, v12.4s, v13.s[1]
  sqdmlsl2 v4.2d, v12.4s, v13.s[1]
  sqdmlsl2 v5.2d, v12.4s, v13.s[1]
  sqdmlsl2 v6.2d, v12.4s, v13.s[1]
  sqdmlsl2 v7.2d, v12.4s, v13.s[1]
  sqdmlsl2 v8.2d, v12.4s, v13.s[1]
  sqdmlsl2 v9.2d, v12.4s, v13.s[1]
  sqdmlsl2 v10.2d, v12.4s, v13.s[1]
  sqdmlsl2 v11.2d, v12.4s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30133	225	0	17	104	0	25	120100	100	120000	100	120000	500	960000	0	30020	0	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	1	0	7610	1	16	1	1	30036	120000	100	30040	30043	30040	30040	30040
120204	30039	225	0	0	41	6671	25	120101	100	120000	100	120000	500	960000	0	30020	0	30039	30042	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	1	7610	1	16	1	1	30036	120000	100	30040	30923	30040	30040	30040
120204	30039	231	0	0	44	0	25	120100	100	120017	100	120000	500	960000	0	30020	0	30040	30039	14973	3	14997	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30039	120000	100	30040	30944	30040	30040	30040
120204	30039	225	0	35	41	0	25	120100	100	120000	100	120000	500	4283400	0	30020	0	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30944	30040	30043
120204	30039	225	0	0	44	3405	25	120100	100	120017	100	120000	500	960000	0	30924	0	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30040	30534
120204	30039	225	0	53	61	3405	25	120100	100	120001	100	120000	500	960000	0	30023	0	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30040	30040
120204	30039	225	0	0	124	0	25	120100	100	120001	100	120000	500	4283622	1	30903	0	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30944	30040	30040	30040
120204	30039	231	0	1	41	0	25	120100	100	120000	100	120000	500	960000	1	30020	0	30039	30042	14973	3	14997	120100	200	120000	200	360000	30039	30042	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30043	30040	30040	30040
120204	30039	225	0	17	44	0	25	120100	100	120001	100	120000	500	960000	1	30924	0	30039	30089	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30043	30040	30040	30040
120204	30039	225	0	0	41	0	25	120101	100	120000	100	120000	500	960000	0	30020	0	30042	30039	14973	3	14997	120100	200	120000	200	360000	30039	30922	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	30036	120000	100	30040	30923	30040	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30050	229	0	0	0	0	0	0	0	0	0	141	0	25	120010	10	120000	10	120000	50	960000	0	0	30020	0	30039	30042	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7522	6	1	2	7	16	4	2	2	6	4	30036	0	30	5	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	1	30020	0	30039	30039	14996	3	15020	120010	20	120000	20	360000	30039	31750	1	1	120021	10	9	10	10	120000	10	0	0	0	0	2	0	0	0	7524	6	2	1	4	16	4	2	2	6	4	30036	0	30	10	120000	10	30040	30041	30041	31751	30041
120024	30039	238	0	0	0	0	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	1	0	30020	0	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	6	2	2	6	16	4	2	2	4	6	30036	0	30	10	120000	10	30041	30040	30040	30040	30040
120024	30040	225	0	0	0	0	0	0	0	0	0	46	0	25	120010	10	120035	10	120000	50	960000	0	1	30020	0	30951	30039	14996	3	15019	120010	20	120000	20	360000	30040	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	30	0	0	0	7524	6	2	2	6	16	2	2	2	4	6	30036	0	15	10	120000	10	30040	30040	30040	31751	30040
120024	30039	224	0	0	0	0	0	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	0	0	30020	0	31750	30039	14996	25	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	3	1	1	5	16	4	1	2	6	4	30036	0	30	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	0	30903	0	30039	31750	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	6	5	2	6	16	4	2	2	6	4	30036	0	30	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	4402296	0	1	30020	0	30039	30951	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	6	2	2	6	16	4	2	2	6	4	30036	0	99	10	120000	10	30040	30040	30040	30040	30040
120024	30040	225	0	0	0	0	0	12	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	0	30020	0	30039	30039	14996	3	15019	120010	20	120000	20	360000	31750	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	6	2	2	6	16	4	2	2	4	6	30036	0	30	20	120000	10	30040	30040	30943	30040	30040
120024	30039	225	0	0	0	0	0	21	0	0	0	52	3489	25	120062	10	120052	10	120000	50	4394061	0	0	31731	0	30039	30040	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	1	0	0	0	7524	6	2	2	6	16	4	2	2	6	4	30036	0	30	10	120000	10	30040	30040	31751	30041	31751
120024	31750	225	0	0	0	0	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	1	30932	0	30039	30039	14996	3	15019	120010	20	120000	20	360000	30951	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7524	6	2	2	6	16	4	2	2	4	6	30036	0	30	10	120000	10	30040	30040	30043	30041	30041

SQDMLSL2 (by element, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations