Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL2 (vector, 2D)

Test 1: uops

Code:

  sqdmlsl2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303722000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303723000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
100430372200001320612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038
1004303722000000612548251000100010003983131301830373037241532895100010003000303730371110011000000000073216222630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqdmlsl2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313030018300373003728272728740101002001000820030024300373003711102011009910010010000100090111717011600296460100001003003830038300383003830038
10204300372240006129548251011010210000100100005004277313030018300373003728272728740101002001000820030024300373003711102011009910010010000100060111718001600296460100001003003830038300383003830038
102043003722500050629548251010010010000100100005004277313130018300373003728272728741101002001000820030024300373003711102011009910010010000100030111717001600296460100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372827262874110100200100082003002430037300371110201100991001001000010001860111717001600296470100001003003830038300383003830038
1020430037225000726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000270000710121622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000600000710121622296340100001003003830038300383003830038
10204300372260006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000000710121622296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000870000710121622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010001110000710121622296340100001003003830038300383003830038
10204300372240008229548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000710131622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000156295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640217222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225100103295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037224000103295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqdmlsl2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250912954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722408102954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250892954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010027101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000001506402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001006402162229668010000103003830038300383003830088
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830226
1002430037226000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000541206402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100002006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqdmlsl2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500001472954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500005672954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500004912954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500004972954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500001262954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500005222954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500005112954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
102043003722500005272954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500004102954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006404162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300841110021109101010000100006402162229630010000103003830038300383003830038
1002430037225015061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000103295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  sqdmlsl2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  sqdmlsl2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  sqdmlsl2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  sqdmlsl2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  sqdmlsl2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  sqdmlsl2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  sqdmlsl2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200651500020925801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
16020420064150006025801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
16020420064150003925801001008000010080000500640000120045200642006403228010020080000200240000200642006411160201100991001001600001001010112216242006101600001002006520065200652006520065
16020420064150003925801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
16020420064150006025801001008000010080000500640000020045200642006403228024620080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
16020420064150003925801001008000010080000500640000020045200642006453228010020080000200240000200642006411160201100991001001600001000310159216222006101600001002006520065200652006520065
160204200641530016525801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112350222006101600001002006520065200652006520065
160204200641500014425801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
160204200641500055125801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216222006101600001002006520065200652006520065
16020420064151008125801001008000010080000500640000020045200642006403228010020080000200240000200642006411160201100991001001600001000010112216432006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03183f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420097150038332780012128000012800006264000010200322005120051322800122080000202400002005120051111600211091010160000101010030311925211820200612201160000102006120061200522005220052
16002420051150070427800121280000128000062640000112003220051200513228001220800002024000020051200511116002110910101600001000100443116252112020200612201160000102005220052200522005220052
160024200601500452780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100010043311825211916200612201160000102005220052200522005220052
16002420051150010827800121280000128000062640000112003220051200513228001220800002024000020051200511116002110910101600001050100433111925421819200832401160000102005220052200522005220052
1600242005115004527800121280000128000062640000112003220051200513228001220800002024000020051200511116002110910101600001000100433111625211196200832201160000102005220052200522005220052
160024200511500129278001212800001280000626400001020032200512005132280012208000020240000200512005111160021109101016000010001004331119252111919200832201160000102005220052200522005220052
160024200511500662780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100010032311825211819200832201160000102005220052200522005220052
1600242005115001292780012128000012800006264000010200322005120051322800122080000202400002005120051111600211091010160000100010032311825211198200612201160000102005220052200522005220052
160024200511500662780012128000012800006264000011200322005120051322800122080000202400002005120051111600211091010160000100010043311825211819200832201160000102005220052200522005220052
1600242005115001752780012128000012800006264000010200322005120051322800122080000202400002005120051111600211091010160000100010030311825211198200832201160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  sqdmlsl2 v0.2d, v16.4s, v17.4s
  sqdmlsl2 v1.2d, v16.4s, v17.4s
  sqdmlsl2 v2.2d, v16.4s, v17.4s
  sqdmlsl2 v3.2d, v16.4s, v17.4s
  sqdmlsl2 v4.2d, v16.4s, v17.4s
  sqdmlsl2 v5.2d, v16.4s, v17.4s
  sqdmlsl2 v6.2d, v16.4s, v17.4s
  sqdmlsl2 v7.2d, v16.4s, v17.4s
  sqdmlsl2 v8.2d, v16.4s, v17.4s
  sqdmlsl2 v9.2d, v16.4s, v17.4s
  sqdmlsl2 v10.2d, v16.4s, v17.4s
  sqdmlsl2 v11.2d, v16.4s, v17.4s
  sqdmlsl2 v12.2d, v16.4s, v17.4s
  sqdmlsl2 v13.2d, v16.4s, v17.4s
  sqdmlsl2 v14.2d, v16.4s, v17.4s
  sqdmlsl2 v15.2d, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044006830000000000410251601011001600011001600005001280000040030040040400391997303199971601002001600002004800004004040039111602011009910010016000010000000001011022973240320211600001004155840966400404004940049
1602044004831311141327721980304029488312161876123161719128162533613199777004104604102340893202370752055916218320816214420448600341190412942311602011009910010016000010030803500001043921951140778221600001004122541470412214122340967
1602044157231810161318637925031427735466162482120161809124161963616173990404065504057640712201420762036016082120016000020048000040048400391116020110099100100160000100000002110118016004003701600001004004940050400404004040040
16020440048300000000003002516010810016000810016002050012801321400200400394003919977061999016012020016003220048009640039400481116020110099100100160000100000011110118016004003601600001004004040040400404004040040
16020440039300000000003002516010810016000810016002050012801320400200400394003919977061999016012020016003220048009640039400391116020110099100100160000100010011110118016114003601600001004004040049400404004040040
160204400393000000001705002516011710016000010016000050012800000400200400484003919973031999716010020016000020048000040048400481116020110099100100160000100000000010110116114003601600001004004040040400494004040040
160204400393000000001704102516011710016000010016000050012800000400200400484003919973031999716010020016000020048000040048400481116020110099100100160000100000000010110116114003601600001004004040040400494004040049
16020440039300000000005002516010010016000010016000050023989991400300400394003919973031999716010020016000020048000040048400391116020110099100100160000100000000010110116114004501600001004004040040400494004040049
16020440039300000000005002516010010016000010016000050023989990400290400484004819973032000616010020216000020048000040048400391116020110099100100160000100000000010110116114003601600001004004040050400414004040049
160204400493000000000070602516010010016001710016000050012800001400200400394003919973031999716010020016000020048000040039400481116020110099100100160000100000000010110116114003601600001004004940049400494004940040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0318191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244004930000001242516001010160000101600005012800001104002940048400391999632002816001020160000204800004004840039111600211091010160000100000100223222016422132040045305160000104004940040400504004040049
1600244004830000017552516002710160017101600005012800000154002040039400391999632001916001020160000204800004003940048111600211091010160000100000100228211316211142840045155160000104004040049400404004040040
16002440048300000174625160027101600171016000050128000011540029400484003919996320028160010201600002048000040048400391116002110910101600001000001002211211216212103240036305160000104004040049400404004040049
16002440039300000177202516001010160000101600005023989991154002940039400391999632001916001020160000204800004004840039111600211091010160000100000100228211316211112440045155160000104004940040400494004040049
1600244003930000017552516002710160017101600005012800001154002040039400481999632002816001020160000204800004003940039111600211091010160000100000100248211916211112440045155160000104004040049400404010940040
1600244003929900017552516002710160017101600005012800001154002940048400391999632001916001020160000204800004004840039111600211091010160000100000100228211916211142840036305160000104004040049400404004040049
1600244004930000017462516002710160000101600005012800001154002940039400481999632002816001020160000204800004004840039111600211091010160000100000100228211416211192340045155160000104004940040400404004040040
160024400393000000462516001010160000101600005023989991154002940048400391999632001916001020160000204800004004840039111600211091010160000100000100228311916412182240036455160000104004940040400494004040040
160024400393000000882516002710160017101600005012800000154002940048400391999632002816001020160000204800004003940048111600211091010160000100000100228211316211132340036155160000104004940040400494004040049
160024400393000000522516001010160000101600005023989991154007940039400481999632001916001020160000204800004004840039111600211091010160000100000100228312016411202640036155160000104004940040400494004040049