Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL2 (vector, 4S)

Test 1: uops

Code:

  sqdmlsl2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001008100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000253573116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000973116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723060625482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303722021625482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqdmlsl2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722510100006129548251010010010000100100005004277313030018300373003728272062876010251200100082003002430037300371110201100991001001000010000111717011621296510100001003003830038300383003830038
102043003722510100006129548251010010010000100100005004277313130018300373003728272072874010100200100082003002430037300371110201100991001001000010000111718011611296510100001003003830038300383003830038
102043003722510100008929548251010010010000100100005004277313030018300373003728272072874110100200100082003002430037300371110201100991001001000010000111720011611296510100001003003830038300383003830038
102043003722510100006129548251010010010000100100005004277313130018300373003728272062874110100200100082003002430037300371110201100991001001000010000111718011611296510100001003003830038300383003830038
10204300372251010000293295482510100100100001001000050042773130300183003730037282650252874510100200100002003000030037300371110201100991001001000010000000710141633296340100001003003830038300383003830038
102043007422500020006129548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000000710131633296340100001003003830038300383003830038
1020430037225000000053629548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000000710131633296340100001003003830038300383003830038
1020430037225000000072629548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000010710131633296340100001003003830038300383003830038
1020430037225000000163129548251013010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000000710131633296340100001003003830038300383003830038
1020430037225000000072629548251010010010000100100005004277313030018300373003728265032874510100200100002003000030037300371110201100991001001000010000000710131633296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020300003003730037111002110910101000010000640216332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020300003003730037111002110910101000010000640216322963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
1002430037225006129548251001010100071010000504277313130018030037300372828732876710010201000020300003003730037111002110910101000010000640316222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640316232963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216232963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018330037300372828732876710010201000020300003003730037111002110910101000010000640216332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020300003003730037111002110910101000010000640216342963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313130018030037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018030037300372828732876710010201000020300003003730037111002110910101000010000640216232963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqdmlsl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225026761295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300623003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372251061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828702628767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqdmlsl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001803003730037282653287451010020010180200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372244950612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372256036129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282893287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372245376129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372254776129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372257566129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001030640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  sqdmlsl2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  sqdmlsl2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  sqdmlsl2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  sqdmlsl2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  sqdmlsl2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  sqdmlsl2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  sqdmlsl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200891500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000000101189161010200611600001002006520065200652006520065
160204200641501539258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000241011991699200611600001002006520065200652006520065
160204200641501839258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000910119111699200611600001002006520065200652006520065
16020420064150153925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000001011891698200611600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000001011841689200611600001002006520065200652006520065
16020420064150013425801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010000001012091694200611600001002006520065200652006520065
1602042006415015392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000101209161010200611600001002006520065201342006520065
16020420064150153925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010000001011991699200611600001002006520065200652006520065
16020420064150963925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000001011991699200611600001002006520065200652006520065
16020420064151123925801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010000001011491699200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006415095125800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100273114204114420043215160000102004720047200472004720047
1600242004615094525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100263113202113420043215160000102004720047200472004720047
160024200461504414525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100273113202113420043230160000102004720047200472004720047
160024200461503034525800121280000128000062640000012002720046200463228001220800002024000020046200461116002110910101600001000100273113202214320043215160000102004720047200472004720047
160024200461503124525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100273114202114320043215160000102004720047200472004720047
1600242004615004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100303114202213420043215160000102004720047200472004720047
1600242004615004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100263113202114320043215160000102004720047200472004720047
16002420046150013925800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001020100263113202113420043215160000102004720047200472004720047
16002420046150244525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100266114202114320043215160000102004720047200472004720047
1600242004615004525800121280000128000062640000112002720046200463228001220800002024000020050200461116002110910101600001000100273114202114420043215160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  sqdmlsl2 v0.4s, v16.8h, v17.8h
  sqdmlsl2 v1.4s, v16.8h, v17.8h
  sqdmlsl2 v2.4s, v16.8h, v17.8h
  sqdmlsl2 v3.4s, v16.8h, v17.8h
  sqdmlsl2 v4.4s, v16.8h, v17.8h
  sqdmlsl2 v5.4s, v16.8h, v17.8h
  sqdmlsl2 v6.4s, v16.8h, v17.8h
  sqdmlsl2 v7.4s, v16.8h, v17.8h
  sqdmlsl2 v8.4s, v16.8h, v17.8h
  sqdmlsl2 v9.4s, v16.8h, v17.8h
  sqdmlsl2 v10.4s, v16.8h, v17.8h
  sqdmlsl2 v11.4s, v16.8h, v17.8h
  sqdmlsl2 v12.4s, v16.8h, v17.8h
  sqdmlsl2 v13.4s, v16.8h, v17.8h
  sqdmlsl2 v14.4s, v16.8h, v17.8h
  sqdmlsl2 v15.4s, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044003930000000004102516010010016000010016000050012800001400204003940048199733199971601002001600002004800004003940039111602011009910010016000010000100010110216224003601600001004004940040400404004040040
1602044003930000000007062202516010010016000010016000050012800001400204003940039199913199971601002001600002004800004003940039111602011009910010016000010000000010110216224003601600001004004940040400404004040049
16020440039300000120004102516010010016000010016000050012800001400204003940039199733199971601002001600002004800004004840039111602011009910010016000010000000010110216224003601600001004004040040400404004040040
1602044003930201000004102516010010016000010016000050013044121400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000000010110216224003601600001004004940179400404004040049
1602044003930000000004102516010010016000010016000050012800001400294003940039199733199971601002001600002004800004003940039111602011009910010016000010000000010110216224003661600001004004040049400404004940040
16020440039300000000011302516011710016000010016000050012800000400204003940039199733199971601002001600002004800004004840039111602011009910010016000010000000010110216224003601600001004004040049400404004040040
1602044003930000000004102516010010016001710016000050012800001400204003940039199733200061601002001600002004800004003940039111602011009910010016000010000000910110216224003601600001004004040040400404004940040
1602044003930000051880070602516011710016001710016000050012800001400204019240039199733199971601002001600002004800004003940039111602011009910010016000010000000010110216224003601600001004004040049400404004040040
1602044003930000000005002516010010016000010316000050012800001400204003940039199733199971601002001600002004800004003940048111602011009910010016000010000000010110216224003601600001004004040040400494004040040
1602044003930000400004102516011710016000010016000050012800001400204004840039199733200061601002001600002004800004003940048111602011009910010016000010000000010110216224003601600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03191e1f373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244004830007800046251600101016000010160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000100010024622416422444003603010160000104004040040400414004940040
1600244003930003000052251600271016000010160000502438865014002040039400491999632001916001020160000204800004003940039111600211091010160000100010024622316422434003603010160000104004040040400404004040040
1600244003930005490005625160010101600001016000050131651411400204003940039199963200201600102016000020480000400394003911160021109101016000010001002231141621134400360155160000104004040040400404004040040
160024400393000900071225160010101600001016000050128000011400204003940040199963200191600102016000020480000400394003911160021109101016000010001002231141621134400460156160000104004040040400504004040040
1600244003930002400056251600101016000010160000502438865114002040039400391999632001916001020160000204800004003940039111600211091010160000100010024621316422444003603010160000104004040040400404004040040
1600244003930006300052251600281016000010160000501280000014002040039400391999632001916001020160000204800004003940039111600211091010160000100010022622416225344003603010160000104004040040400404004040040
160024400393000900052251600101016000010160000501280000014003040039400391999632001916001020160000204800004003940039111600211091010160000100010024625316422344003603010160000104004040040400504004040040
16002440039300033300052251600101216000010160000502438865014002940039400391999632002916001020160000204800004004940039111600211091010160000100010024622416422434003603010160000104004940040400504005040050
1600244003930002700046251600101016000010160000501280000014002040039400391999632001916001020160140204800004003940039111600211091010160000100010024622416422434003603012160000104004040040400404004040050
1600244004930001050005325160010101600181016000050128000001400204004040048199963200191600102016000020480000400394003911160021109101016000010001002231141621134400360155160000104005040050400404004040040