Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL (scalar, D)

Test 1: uops

Code:

  sqdmlsl d0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
1004303723013561254825100010001000398313030183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037220961254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
100430372300230254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
100430372306061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100000073216222630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqdmlsl d0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224100001200612954825101001001000010010000500427731330018300853003728265728762101002001000020030000300373003711102011009910010010000100000000712131633296340100001003003830038300383003830038
102043003722500000000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100200000732131633296340100001003003830038300383003830086
102043003722500000000103294851441017912510024124108946214286081302703037230371282874128870110112181116322433465301323036981102011009910010010000100222660195668681472542989111100001003037230324303723037230373
1020430370227011779365282454129485144101681221006412511043626428545530270303603032228291352887211018224111592263346230417303717110201100991001001000010000005202938711372352988712100001003037230370303713046730469
102043041822800169119779215216294761801019012610072125111926264290774303423046330512283005028892114662301132422634242304193041881102011009910010010000100000000710131633298690100001003003830038300383003830038
102043003722500000000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000103710131633296340100001003003830038300383003830038
1020430037224000001200612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000100710131633296340100001003003830038300383003830038
102043003722500000000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000000710131633296340100001003003830038300383003830038
10204300372250000000061295382510100100100081041000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000010135710131633296340100001003003830038300383003830038
102043003722500000000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000000710131633296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722524661295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640217222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqdmlsl d0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001059650042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100107101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250726295482510100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001004867101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001029850042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100037101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001004137101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001005007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001006307101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001004107101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000060640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000560640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000003640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830083
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010020446640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100005718640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000563640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000093640216222963010000103003830038300383003830038
100243003722500061295482510010101000010105965042773130300183003730037282873287671001020100002030000300373003711100211091010100001020000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqdmlsl d0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038
1020430037224072629548251010010010000100100005004277313030054300843008428265328745101002001000020030996301333008521102011009910010010000100242002408520710216222963412100001003008530085300863003830086
102043008522665992954825101001001000010010149500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296670100001003003830038300893003830038
102043003722501032954844101001001000010010000500427867013001830037300372826532874510100200100002003000030037300371110201100991001001000010000200030071021622296340100001003003830038300383003830038
10204300372250822954825101001001000010010000500427731313001830037300372827632874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038
1020430037225010329548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000000000710216222963429100001003003830038300383003830038
102043003722512612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830082
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000810100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl d0, s8, s9
  movi v1.16b, 0
  sqdmlsl d1, s8, s9
  movi v2.16b, 0
  sqdmlsl d2, s8, s9
  movi v3.16b, 0
  sqdmlsl d3, s8, s9
  movi v4.16b, 0
  sqdmlsl d4, s8, s9
  movi v5.16b, 0
  sqdmlsl d5, s8, s9
  movi v6.16b, 0
  sqdmlsl d6, s8, s9
  movi v7.16b, 0
  sqdmlsl d7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009115110000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112316222006101600001002006520065200652006520065
1602042006415100000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
16020420064151000000000324258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
1602042006415000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
16020420064151000000000439258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
1602042006415000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
1602042006415000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
1602042006415000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000003010112216222006101600001002006520065200652006520065
1602042006415000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065
1602042006415100000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010112216222006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200801500003192580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278215202113420043264160000102004720047200472004720047
160024200461500002342580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202114320043232160000102004720047200472004720047
160024200501500007092580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000300100278214202114320043264160000102004720047200472004720047
160024200501500002162580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202113420043264160000102004720047200472004720047
160024200461500002562580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202113420043264160000102004720047200472004720047
160024200461500002682580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010001300100268213202113420043232160000102004720047200472004720047
160024200461500002482580012128000012800006264000011520027200462004632280012208000020240000200462004811160021109101016000010000000100268214202114320043264160000102004720047200472004720047
160024200461500002232580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202114320043232160000102004720047200472004720047
160024200461500002402580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202114320043232160000102004720047200472004720047
160024200461500002682580012128000012800006264000011520027200462004632280012208000020240000200462004611160021109101016000010000000100278214202114320043264160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  sqdmlsl d0, s16, s17
  sqdmlsl d1, s16, s17
  sqdmlsl d2, s16, s17
  sqdmlsl d3, s16, s17
  sqdmlsl d4, s16, s17
  sqdmlsl d5, s16, s17
  sqdmlsl d6, s16, s17
  sqdmlsl d7, s16, s17
  sqdmlsl d8, s16, s17
  sqdmlsl d9, s16, s17
  sqdmlsl d10, s16, s17
  sqdmlsl d11, s16, s17
  sqdmlsl d12, s16, s17
  sqdmlsl d13, s16, s17
  sqdmlsl d14, s16, s17
  sqdmlsl d15, s16, s17
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)191e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044003930010100004900251601001001600171001600005002398999140029400484003919973319997160100200160000200480000400394004811160201100991001001600001000010114131614144004601600001004004140050400504005340040
160204400493001010001721530251601001001600001001600005001320000140020400394004919973320029160100200160000200480000400394004911160201100991001001600001000010114121614124004501600001004004040049400404004940040
16020440049300101000172570251601001001600011001600005002398999040021400394007119973320029160100200160000200480000400394004911160201100991001001600001000222510114121614124003701600001004004140040400404005040072
1602044003930010100002570251601001001600001001600005002398999140112400394012019973820060160100200160000200480000400394003911160201100991001001600001000010114121614154003601600001004004140040400414004040040
16020440071300101000612790251601001001600171001600005001280000140030400394004819973320006160100200160000200480000400394007111160201100991001001600001000010114141613114003601600001004004140040400404005040041
16020440039299101000172580251601001001600171001600005001320000140052400394003919973319998160100200160000200480000400394004011160201100991001001600001000010114121614124003601600001004004940040400404004940049
160204400483001010001724390251601001001600001001600005002399027140020400494003919973319997160100200160000200480000400394004911160201100991001001600001000010114121614124003601600001004007240049400724004940040
16020440039300101000024925251601611001600611001600005002398999140029400394003919973320006160100200160000200480000400394003911160201100991001001600001000010114111610144003601600001004004040040400494004040040
1602044003930010100002333025160117100160017100160000500128000014002040039400401997331999816010020016000020048000040039400401116020110099100100160000100001011471614104003601600001004005040040400404005040040
1602044004830010100002490251601001001600001001600005002399027140020400494003919973320007160100200160000200480000400494003911160201100991001001600001000010114141614144003601600001004004040040400504004040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244004930000682516001010160000101600005012800001154002004003940039199963200281600102016000020480000400394003911160021109101016000010069401002283181621144402152070160000104004040040400404004040040
160024400393001209225160010101600001016000050128000011540020040039400491999632002916001020160000204800004003940039111600211091010160000100001002283161621144400362060160000104004040040400404004040049
1600244003930024039725160010101600001016000050128000011540020040039400391999632001916001020160000204800004003940039111600211091010160000100001002283131621166400364070160000104004040040400404004040040
1600244004030001710172516001010160000101600005012800000154002004003940039199963200191600102016000020480000400394003911160021109101016000010000100241142616422644003640120160000104004040040400404004040040
16002440039300015902516001010160000101600005024388650154002004003940039199963200191600102016000020480000400394003911160021109101016000010000100241141416422434003658140160000104004040041400494004040040
1600244003930001894251600101016000010160000501280000015400200400394003919996320019160010201601682048000040049400391116002110910101600001000010022831416211664003640120160000104004040040400504004040040
1600244003930000260251600101016000010160000502438865015400290400394003919996320028160010201600002048000040039400391116002110910101600001000010022831616211344003640120160000104004040040400994005040040
1600244003930000467511600101016000010160000501280000115400200400394010119996320019160010201600002048000040040400391116002110910101600001010010022821316211344003640120160000104004940109400494004940041
160024400392990046425160010101600001016000060128000011540020040048400391999632001916001020160000204800004003940039111600211091010160000100001002283161621167400362060160000104004040050400404004140040
16002440039300004625160010101600181016000050128000011540020040039400391999632001916001020160000204800004003940039111600211091010160000100601002283161621143400452090160000104004040040400404004040040