Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL (scalar, S)

Test 1: uops

Code:

  sqdmlsl s0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313130183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010003000303730371110011000005173116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000300030373037111001100000373116112630100030383038303830383038
1004303723082254825100010001000398313130183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
10043037230145254825100010001000398313130183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000300030373037111001100000373116112630100030383038303830383038
1004303723082254825100010001000398313130183037303724153289510001000300030373037111001100001073116112630100030383038303830383038
100430372202492548251000100010003983131301830373037241532895100010003000303730371110011000002773116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000300030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqdmlsl s0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071002162229644100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071002162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071002162329634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071012162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071212162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071012162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071012163229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000021230000300373003711102011009910010010000100071012162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071012162229634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640316222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000103640216322963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225036129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216232963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372240156129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216322963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000103640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqdmlsl s0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000021630000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000500071011611296340100001003003830038300383003830038
10204300372330000096129538251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000020071012511296340100001003003830038300383003830038
102043003723300000082295482510100100100001001014950042773130300183003730037282653287451010020010167200300003003730037111020110099100100100001000000007893380222996930100001003042030455304223042630417
102043041923611087080512954825101001001000013010000500427731313001830037300372826532874510408200100002063000030037300371110201100991001001000010000010111550873116112978629100001003003830038304723018430470
102043065523300116098329548251010010010000100100005004277313030018300373003728265328745101002001000020031488300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500015006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006404162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100050006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203048930037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqdmlsl s0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722502256129548251010010010000100100005004277313103001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
10204300372250366129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300376110201100991001001000010000271051161129634100001003003830038300383003830038
10204300372240306129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071051161129634100001003003830038300383003830038
10204300372240456129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
10204300372250216129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071051161129634100001003003830038300383003830038
10204300372250156129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071051161129634100001003003830038300383003830038
1020430037225115251295482510100100100001001000050042773130530018300373003728265122874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
10204300372240396129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071051161129634100001003003830038300383003830038
102043003722502376129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500558929548251010010010000100100005004277313053001830037300372826532874510100200100002003000030037300371110201100991001001000010000071051161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427779730018300373003728287328767100102010000203048330037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372240000001612953925100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300372110021109101010000100000000006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl s0, h8, h9
  movi v1.16b, 0
  sqdmlsl s1, h8, h9
  movi v2.16b, 0
  sqdmlsl s2, h8, h9
  movi v3.16b, 0
  sqdmlsl s3, h8, h9
  movi v4.16b, 0
  sqdmlsl s4, h8, h9
  movi v5.16b, 0
  sqdmlsl s5, h8, h9
  movi v6.16b, 0
  sqdmlsl s6, h8, h9
  movi v7.16b, 0
  sqdmlsl s7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420088151002403712580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000010127151614142006101600001002006520065200652006520065
16020420064150103304712580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000000010126141613152006101600001002006520065200652006520065
1602042006415110003712580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000000010126141614142006101600001002006520065200652006520065
160204200641500012603544258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000001012012166132006101600001002006520065200652006520065
1602042006415010004712580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000010126121614152006101600001002006520065200652006520065
160204200641500060471258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000001012513166132006101600001002006520065200652006520065
160204200641501000491258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000001012714161472006101600001002006520065200652006520065
1602042006415010004982580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000000010126141614142006101600001002006520065200652006520065
1602042006415010004692580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000000010127141614142006101600001002006520065200652006520065
1602042006415010003462580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000010127121614152006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420068150300300090373278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001005482129252112323200550201160000102005920059200592005920059
16002420058150300300000367278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001005183124252112425200550201160000102005920059200592005920059
160024200581504004000870367278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001004983126252112625200550201160000102005920148200592005920059
16002420058150400400000373278001010800001080000506400000152003920058200583228001020800002024000020058200581116002110910101600001000000001005182124252112024200550201160000102005920059200592005920059
16002420058151200500000373278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001005082125252112523200550201160000102005920059200592005920059
160024200581504003000270373278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001005382126252112323200550201160000102005920059200592005920059
160024200581504004000540367278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001004882119252112622200550201160000102005920059200592005920059
160024200581504002000270373278001010800001080000506400001152003920058200583228001020800002024000020058202971116002110910101600001000000001005182123252112424200550201160000102006820068200592005920059
160024200581504004000420373278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001005282122252111720200550201160000102005920059200592005920059
160024200581503003000570367278001010800001080000506400001152003920058200583228001020800002024000020058200581116002110910101600001000000001004082125252112423200550201160000102005920059200592005920059

Test 6: throughput

Count: 16

Code:

  sqdmlsl s0, h16, h17
  sqdmlsl s1, h16, h17
  sqdmlsl s2, h16, h17
  sqdmlsl s3, h16, h17
  sqdmlsl s4, h16, h17
  sqdmlsl s5, h16, h17
  sqdmlsl s6, h16, h17
  sqdmlsl s7, h16, h17
  sqdmlsl s8, h16, h17
  sqdmlsl s9, h16, h17
  sqdmlsl s10, h16, h17
  sqdmlsl s11, h16, h17
  sqdmlsl s12, h16, h17
  sqdmlsl s13, h16, h17
  sqdmlsl s14, h16, h17
  sqdmlsl s15, h16, h17
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044005930000001170184102516010010016000010016000050012800000040020400494004919973032000716010020016000020048000040039400391116020110099100100160000100000400001011002161140036001600001004004040040400404004040050
16020440049300000012004102516010010016000010016000050012800000040020400394003919973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140036001600001004004040040400404004040040
1602044003930100000004102516010010016000010016000050012800000040020400494004919973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140036001600001004004040040400404004040050
1602044003929900000004102516010010016000010016000050012800000040020400494004919973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140036001600001004004040040400404004040040
16020440040300000000185102516010010016000010016000050012800001040029400394003919973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140036001600001004004040041400404004040040
1602044003929900000004102516010010016000010016000050012800000040020400494004919973031999716010020016000020048000040039400481116020110099100100160000100000000001011001161140036001600001004004040049400494004040049
1602044003930000000004102516010010016000010016000050012800000040020400394003919973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140036001600001004004040040400404004040040
1602044003930000000004102516010010016000010016000050012800000040020400394004819973031999716010020016000020048000040039400391116020110099100100160000100000000001011001161140046001600001004004040040400404004040040
1602044003930000009004105016011810016000010016000050012800000040020400404004819973031999716010020016000020048000040048400391116020110099100100160000100000000001011001161140036401600001004005040050400504005040040
1602044003930000000004102516010010016000010016000050012800000140030400394009819973032000716010020016000020048000040039400391116020110099100100160000100000001750001011001161140085001600001004005040050400504005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400483000601755025160027101600171016000050128000011400204004840048199963200281600102016000020480000400484004811160021109101016000010001002231121162116154004501510160000104004040049400404004940040
16002440039300024004602516001010160000101600005023989991140029400394004819996320028160010201600002048000040048400391116002110910101600001000100223111016211511400450155160000104004940049400494004940049
1600244004830003001715032516001010160000101600005023989991140020400394004819996320028160010201600002048000040048400391116002110910101600001000100223111516211127400360155160000104004040049400494004040049
1600244004830006017550251600271016000010160000502398999114002040039400481999632002816001020160000204800004003940048111600211091010160000100010022311816211146400360155160000104004940040400494004040049
16002440048300033017550251600271016001710160000501319997114002940052400481999632001916001020160000204800004003940048111600211091010160000100010022311516211716400360155160000104004940040400494004040049
1600244004830000017550251600271016000010160000501280000114002040039400481999632002816001020160000204800004004840039111600211091010160000100010022311916211614400450155160000104004940049400494004940040
1600244003930009017460251600101016001710160000502398999114002040048400391999632002816001020160000204800004003940048111600211091010160000100010022311121621199400450155160000104004040040400404004040049
1600244004830003001746025160010101600001016000050239899911400294004840048199963200191600102016000020480000400484003911160021109101016000010001002231191621195400450155160000104004040049400404004940040
160024400483000360055025160027101600171016000050128000010400294004840039199963200281600102016000020480000400394004811160021109101016000010001002231161621195400450155160000104004940049400404004040040
160024400483000001756025160027101600171016000050128000011400294004940270199963200281600102016000020480000400394004811160021109101016000010001002231191621197400450155160000104004940049400404004940040