Firestorm: SQDMLSL (vector, 2D) measurements

Code:

  sqdmlsl v0.2d, v1.2s, v2.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	124	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	18	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1162	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	54	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqdmlsl v0.2d, v1.2s, v2.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30084	1	1	10201	100	99	100	100	10000	100	0	195	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	710	1	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	159	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	90	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	204	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29668	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqdmlsl v0.2d, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30084	1	1	10201	100	99	100	100	10000	100	0	1	3	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	126	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	9	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	16	6	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	1	3	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	6	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	54	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	0	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	9	710	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	9	661	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	3	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10159	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	105	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	195	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	111	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	54	640	2	16	2	2	29630	10000	10	30133	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30179	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	640	2	16	2	2	29630	10000	10	30418	30419	30414	30415	30359

Test 4: Latency 1->3

Code:

  sqdmlsl v0.2d, v1.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30181	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	84	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	4	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	123	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	39	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	9	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	673	29548	42	10120	100	10000	100	10000	500	4277313	0	30162	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	126	710	1	50	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	527	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30229	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	9	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	231	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	180	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	103	29548	25	10100	100	10000	100	10000	578	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	6	735	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28277	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	11	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	4	0	3	644	8	16	10	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	6	644	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	45	0	0	644	10	16	11	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	3	644	11	16	11	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	28	0	0	644	11	16	11	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	3	644	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	6	644	10	16	11	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	3	644	11	16	10	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	1	0	2	68	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	644	10	16	11	10	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl v0.2d, v8.2s, v9.2s
  movi v1.16b, 0
  sqdmlsl v1.2d, v8.2s, v9.2s
  movi v2.16b, 0
  sqdmlsl v2.2d, v8.2s, v9.2s
  movi v3.16b, 0
  sqdmlsl v3.2d, v8.2s, v9.2s
  movi v4.16b, 0
  sqdmlsl v4.2d, v8.2s, v9.2s
  movi v5.16b, 0
  sqdmlsl v5.2d, v8.2s, v9.2s
  movi v6.16b, 0
  sqdmlsl v6.2d, v8.2s, v9.2s
  movi v7.16b, 0
  sqdmlsl v7.2d, v8.2s, v9.2s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	1	0	104	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	62	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10112	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	60	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	4	0	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80318	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	3	2	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	534	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	6	10113	3	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	467	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	2	16	3	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	62	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10113	2	16	3	3	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20088	150	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	0	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	8	1	1	4	25	2	1	1	4	4	20048	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	51	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	3	2	4	34	4	2	2	6	2	20057	2	40	2	160000	10	20061	20052	20061	20061	20061
160024	20060	150	0	0	51	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	11	3	4	2	34	4	2	2	2	4	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	462	29	80012	12	80000	12	80000	62	640000	0	1	5	20032	20060	20060	3	22	80012	20	80000	20	240000	20060	20051	1	1	160021	10	9	10	10	160000	10	2	0	0	10030	11	3	2	4	34	2	2	2	2	4	20057	2	40	1	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	156	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	4	2	4	34	4	1	2	4	2	20057	2	40	2	160000	10	20052	20061	20052	20061	20061
160024	20060	151	0	0	137	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20051	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	4	2	2	25	4	2	1	2	4	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	151	0	0	116	27	80012	12	80000	12	80000	62	640000	1	1	5	20041	20051	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	4	2	4	34	4	2	2	4	2	20057	2	40	1	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	51	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	11	4	2	4	25	4	2	2	4	2	20057	2	40	2	160000	10	20061	20052	20061	20052	20061
160024	20060	151	0	0	93	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	4	2	6	34	4	2	2	6	4	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	51	0	856	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	4	2	4	34	2	2	1	4	2	20057	2	40	2	160000	10	20061	20061	20061	20061	20062

Test 6: throughput

Count: 16

Code:

  sqdmlsl v0.2d, v16.2s, v17.2s
  sqdmlsl v1.2d, v16.2s, v17.2s
  sqdmlsl v2.2d, v16.2s, v17.2s
  sqdmlsl v3.2d, v16.2s, v17.2s
  sqdmlsl v4.2d, v16.2s, v17.2s
  sqdmlsl v5.2d, v16.2s, v17.2s
  sqdmlsl v6.2d, v16.2s, v17.2s
  sqdmlsl v7.2d, v16.2s, v17.2s
  sqdmlsl v8.2d, v16.2s, v17.2s
  sqdmlsl v9.2d, v16.2s, v17.2s
  sqdmlsl v10.2d, v16.2s, v17.2s
  sqdmlsl v11.2d, v16.2s, v17.2s
  sqdmlsl v12.2d, v16.2s, v17.2s
  sqdmlsl v13.2d, v16.2s, v17.2s
  sqdmlsl v14.2d, v16.2s, v17.2s
  sqdmlsl v15.2d, v16.2s, v17.2s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	311	0	0	140	25	160100	100	160017	100	160000	500	1280000	0	40020	40048	40039	19973	0	3	19998	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	3	4	40036	0	160000	100	40049	40049	40040	40040	40049
160204	40039	300	0	0	50	25	160100	100	160017	100	160000	500	2398999	0	40029	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	3	40036	0	160000	100	40041	40040	40040	40049	40040
160204	40040	300	0	17	171	25	160100	100	160000	100	160000	500	1280000	0	40111	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	4	40036	0	160000	100	40040	40040	40049	40040	40049
160204	40048	300	0	0	41	25	160117	100	160000	100	160000	500	1280000	0	40020	40039	40048	19973	0	3	20006	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	3	40036	0	160000	100	40040	40050	40040	40040	40040
160204	40048	299	0	17	50	25	160117	100	160000	100	160000	500	1280000	0	40029	40039	40039	19973	0	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	3	10110	1	16	1	3	40045	0	160000	100	40040	40049	40040	40040	40040
160204	40039	299	0	0	50	25	160100	100	160000	100	160000	500	1280000	0	40020	40048	40048	19973	0	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40045	0	160000	100	40040	40049	40040	40040	40040
160204	40039	300	0	17	706	25	160100	100	160017	100	160000	500	1280000	0	40020	40039	40039	19973	0	3	20006	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	4	40036	0	160000	100	40040	40040	40049	40040	40040
160204	40039	300	0	0	500	25	160100	100	160000	100	160000	500	2398999	0	40020	40049	40039	19973	0	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	2	40036	0	160000	100	40049	40040	40040	40041	40040
160204	40039	300	0	0	50	25	160100	100	160000	100	160000	500	1280000	0	40020	40039	40048	19973	0	3	20006	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	2	40036	0	160000	100	40040	40049	40049	40049	40049
160204	40048	300	0	1	41	25	160101	100	160000	100	160000	500	2398999	0	40029	40048	40039	19973	0	3	20006	160100	200	160000	200	480000	40048	40048	1	1	160201	100	99	100	100	160000	100	1	6	10110	1	16	1	6	40045	0	160000	100	40040	40049	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	37	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	2	486	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40049	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	2	1	4	16	4	1	1	6	4	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	1	97	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20047	160119	20	160000	20	480000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	2	1	8	16	2	1	1	6	4	40036	0	15	5	160000	10	40050	40050	40040	40040	40040
160024	40039	299	0	0	0	0	0	1	46	25	160027	10	160017	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	11	3	2	6	16	4	2	2	6	4	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40049	300	0	0	0	0	18	2	113	25	160010	10	160017	12	160000	50	2438865	1	1	5	40020	40040	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	3	2	4	16	2	2	2	6	9	40036	0	15	5	160000	10	40040	40040	40040	40040	40040
160024	40040	300	0	0	0	0	0	2	222	25	160010	10	160000	10	160000	50	1280000	0	1	5	40030	40039	40039	19996	0	3	20029	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	2	1	6	16	2	1	1	6	9	40036	0	30	12	160000	10	40040	40049	40049	40049	40040
160024	40039	299	0	0	0	0	18	1	67	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	3	2	4	16	4	2	2	8	6	40036	0	30	10	160000	10	40040	40098	40040	40050	40040
160024	40039	300	0	0	0	0	0	2	504	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	2	1	6	16	4	1	1	6	6	40048	0	30	10	160000	10	40040	40040	40049	40049	40040
160024	40039	300	0	1	0	162	52	2	734	25	160010	10	160000	10	160000	50	1280000	0	1	5	40020	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	2	1	9	16	2	2	1	6	4	40036	0	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	1	111	25	160010	10	160017	10	160000	50	2398999	0	1	5	40029	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	3	1	6	16	4	2	2	8	5	40036	0	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	2	449	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	3	0	0	10022	8	2	2	4	16	4	1	1	8	8	40045	0	30	6	160000	10	40040	40040	40050	40050	40040

SQDMLSL (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations