Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL (vector, 4S)

Test 1: uops

Code:

  sqdmlsl v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372208225482510001000100039831313018303730372415328951000100030003037303711100210000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372296925482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110001073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723017325482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723025725482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqdmlsl v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000064929548251010010010000100100005004277313300180300373003728272728740101002001000820030024300373003711102011009910010010000100000011171801603296460100001003003830038300383003830038
1020430037225000091829548251010010010000100100005434277313300180300373003728272728740101002001000820030024300373003711102011009910010010000100000011171701601296460100001003003830038300383003830038
1020430037225000021929548251010010010000100100005004277313300180300373003728272628741101002001000820030024300373003711102011009910010010000100000011171701600296470100001003003830038300383003830038
1020430037225000010329548251010010010000100100005004277313300180300373003728272728740101002001000820030024300373003711102011009910010010000100200011171801601296460100001003003830038300383003830038
1020430037225100014529548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
102043003722500006129548251014710010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
1020430037225000012429548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
1020430037225000014529548251010010010000100100005114277313300180300373003728265328745101002121000020030000300373003711102011009910010010000100000600071021623296340100001003003830038300383003830038
1020430037224000122129548431010010010000103100005004277313300180300373003728265328745104022081066020030000300373008521102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250300023129548251010010010000100100005004277313300180300373003728265328745101002001000020030000300373022911102011009910010010000100001000071021633296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000000252295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000084295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000161295482510010101000010100005042786701300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000124295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162329688010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000001766295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006401162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqdmlsl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000000124295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000100071021611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300543003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372240000000061295482510100100100001001000063642773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372240000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000015129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000102006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
1002430037225000017029548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
10024300372250015023729548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
1002430037224000012429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
1002430037225000012429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
1002430037225000012429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqdmlsl v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372256900612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722511100612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000107101161129634100001003003830038300383003830038
102043003722536900612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372241200612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250001052954825101001001000010010000500427731313001833003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722539600612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722534500612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722530000612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225001612954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037211020110099100100100001003007101161129634100001003003830038300383003830038
10204300372253900612954825101251041000010010000616427731313009003013230216282657287621010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722541406129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372252706129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722510806129548251001010100081010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001003640216222963010000103003830038300383003830038
100243003722410206129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222969510000103003830038300383003830038
100243003722524606129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722512306129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001010640216222963010000103003830038300383003830038
100243003722525206129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037224993526129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722422206129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722510806129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  sqdmlsl v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  sqdmlsl v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  sqdmlsl v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  sqdmlsl v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  sqdmlsl v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  sqdmlsl v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  sqdmlsl v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420091150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
1602042006415042339258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
1602042006415134239258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322804342008000020024000020064200641116020110099100100160000100010111011611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006415010240356258001212800001280000626400001152002720221200503228001220800002024000020046200461116002110910101600001000100508312620211272420043215160000102004720047200472004720047
1600242004615011120356258001212800001280000626400001152002720208200503228001220800002024000020046200461116002110910101600001000100498312520411242420043215160000102004720047200512004720047
160024200461502260356258001212800001280000626400001152002720197200463228001220800002024000020046200461116002110910101600001000100538412620211192420043215160000102004720047200472004720047
160024200461501100356258001212800001280000626400001152002720150200463228001220800002024000020046200461116002110910101600001000100498312520211202420043215160000102004720047200472004720047
160024200461501100350258001212800001280000626400001152002720190200503228001220800002024000020046200461116002110910101600001000100508412476211262520043215160000102004720047200472004720047
160024200461501000350258001212800001280000626400001152002720156200503228001220800002024000020046200461116002110910101600001000100518412520211242520043215160000102004720047200472004720047
160024200461500060356258001212800001280000626400001152002720143200503228001220800002024000020046200461116002110910101600001000100518412420211211620043215160000102004720047200472004720047
1600242004615021180356258001212800001280000626400001152002720133200503228001220800002024000020046200461116002110910101600001000100528412620211252620043215160000102004720047200472004720047
1600242004615011180356258001212800001280000626400001152002720124200463228001220800002024000020046200461116002110910101600001000100448411820211252120043215160000102004720047200472004720047
160024200461500100356258001212800001280000626400001152002720137200503228001220800002024000020046200461116002110910101600001000100508412420211212620043215160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  sqdmlsl v0.4s, v16.4h, v17.4h
  sqdmlsl v1.4s, v16.4h, v17.4h
  sqdmlsl v2.4s, v16.4h, v17.4h
  sqdmlsl v3.4s, v16.4h, v17.4h
  sqdmlsl v4.4s, v16.4h, v17.4h
  sqdmlsl v5.4s, v16.4h, v17.4h
  sqdmlsl v6.4s, v16.4h, v17.4h
  sqdmlsl v7.4s, v16.4h, v17.4h
  sqdmlsl v8.4s, v16.4h, v17.4h
  sqdmlsl v9.4s, v16.4h, v17.4h
  sqdmlsl v10.4s, v16.4h, v17.4h
  sqdmlsl v11.4s, v16.4h, v17.4h
  sqdmlsl v12.4s, v16.4h, v17.4h
  sqdmlsl v13.4s, v16.4h, v17.4h
  sqdmlsl v14.4s, v16.4h, v17.4h
  sqdmlsl v15.4s, v16.4h, v17.4h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044007730000000017500251601001001600001001600005002398999040020400484003919973320006160100200160000200480000400394003911160201100991001001600001000000010110116114003601600001004004940040400494004040040
160204400393000000000830251601001001600171001600005001319998140020400394003919973320006160100200160000200480000400394003911160201100991001001600001000000310110116114003601600001004004040040400494004040040
160204400393000000000410251601001001600001001600005002398999040020400394003919973319997160100200160000200480000400394003911160201100991001001600001000000010110116114003601600001004004040040400404004040040
160204400393000000000410251601001001600001001600005002398999140020400394003919973319997160100200160000200480000400394003911160201100991001001600001000000010110116114004501600001004004040040400404004040049
160204400393000000000410251601001001600001001600005001319999040020400394003919973319997160100200160000200480000400394003911160201100991001001600001000030010110116114003601600001004004040049400404004040040
1602044003930000000001360251601001001600001001600005002398999140020400394003919973319997160100200160000200480000400394003911160201100991001001600001000000010110116114003601600001004004040040400404004040040
1602044003929900000017410251601011001600001001600005001280000140020400394003919973319997160100200160000200480000400394003911160201100991001001600001000000010110116114003601600001004004040040400404004040040
160204400392990000000410251601001001600001001600005001319997040020400394003919973320006160414200160000200480000401064003911160201100991001001600001000000010110116114003601600001004004040040400404004040040
1602044003930000000017410251601171001600171001600005001280000040020400394003919973319997160100200160000200480000400394004811160201100991001001600001000000010110116114003601600001004004040040400404004040040
16020440039300000000065140251601001001600001001600005001280000140020400394003919973319997160100200160000200480000400394003911160201100991001001600001000000010110116114004501600001004004040040400404004140049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440048300000521025160010101600001016000050128000011540029400394003919996320029160010201600002048000040039400391116002110910101600001010001002282151622174400360305160000104017240040400494004040040
1600244003929910047025160027101600171016000050128000011540089401044003919996112001916011620160208204800004011740039111600211091010160000100000100241131416422554006803010160000104004940072400404004040049
1600244004830000073025160010101600001016000050132000001540052400394003919996320019160010201600002048000040048400391116002110910101600001000001002283151621153400360306160000104004040040400404004940049
160024400493000121788025160010101600611016000050128000011540020400394003919996320028160010201600002048000040039400391116002110910101600001000001004282141621153402160155160000104005040049401004004040040
16002440039299006167025160010101600001016000050128000011540020400394003919996320028160010201600002048000040048400401116002110910101600001000001002282151621135400361156160000104004040049400494004140049
1600244003930001217880251600101616000010160000562398999115400204004840040200363200191604312016051020480000400394007111160021109101016000010215001002282151621153400680155160000104004040040400404004040049
16002440039300060616702516001010160061101600005023989991154002040039400391999332001916001020160000204800004003940048111600211091010160000100300100241132416422874003603010160000104007240040400404004040040
160024400392990909702516001010160000101600005012800001154005240039400401999632001916001020160000204800004003940039111600211091010160000100000100241132716422354003603010160000104004940040400404004040040
1600244003930000052025160010101600001016000050128000001540020400394003919996320028160010201600002048000040039400391116002110910101600001000001002282171621158400360155160000104004040040400404004040040
16002440039300001746025160010101600001016000050128000001540020400394004819996320019160010201600002048000040039400391116002110910101600001000001002282161621164400450155160000104007240040400404004040040