Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMULH (vector, 2S)

Test 1: uops

Code:

  sqdmulh v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372200061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723000191254825100010001000398313030183037303724153289510001000200030373037111001100001073216222630100030383038303830383038
1004303723000335254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722000189254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723000156254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqdmulh v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000410295482510100100100001001000050042773130300183003730037282727287411010020010008200200163003730037111020110099100100100001000000111717016012964613100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313030018300373003728272628741101002001000820020016300373003711102011009910010010000100000011171701601296460100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003721102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000008229548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000014729548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830087
1020430037224000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000012429548251011710010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000027658929548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100010000071011611296340100001003003830038300383003830038
1020430037225000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000073511611296340100001003003830038300383003830038
10204300372250000021929548251010010410000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100003000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722598962954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640316222963010000103003830038300383003830038
10024300372250842954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722401662954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372240842954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222966810000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010030640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722501242954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722501032954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqdmulh v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225002142954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021623296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002036030037300371110201100991001001000010000071021622296340100001003008630038300853008630038
1020430037225001032954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225001052954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021623296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500189295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300853008630038
100243003722500189295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001023006402162329630010000103003830038300383003830038
10024300372252061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000302273003711100211091010100001000006402162329630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162329630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqdmulh v0.2s, v8.2s, v9.2s
  sqdmulh v1.2s, v8.2s, v9.2s
  sqdmulh v2.2s, v8.2s, v9.2s
  sqdmulh v3.2s, v8.2s, v9.2s
  sqdmulh v4.2s, v8.2s, v9.2s
  sqdmulh v5.2s, v8.2s, v9.2s
  sqdmulh v6.2s, v8.2s, v9.2s
  sqdmulh v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100351102161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502041625520036080000102004020040200402004020040
800242003915000000000107258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502061606720036080000102010220040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502041606620036080000102004020040200402004020040
80024200391500001000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000000502051606620036080000102004020040200402004020040
800242003915000000000103258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000000502051605620036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502071605620036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000000502041605520036080000102004020040200402004020040
800242003915000000000515258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000060502051606620036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502061606520036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000000502051605620036080000102004020040200402004020040