Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMULH (vector, 8H)

Test 1: uops

Code:

  sqdmulh v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722126125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722126125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723186125482510001000100039831303018303730372415328951000100020003060303711100110000073116112630100030383038303830383038
1004303722366125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037222496125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723010325482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037233325125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqdmulh v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030f191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
102043003722520002432954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
10204300372240000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963420100001003003830038300383003830038
102043003722500207396612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
102043003722500001612953025101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963411100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963400100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037224000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000066295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
1002430037225007792444014512294941591005914100561610894814280027130270303683032028307332887911056201049024222823036730380811002110910101000010022121025007885903529930310000103038330370304153036930370
100243036822710778045280333329494138100101010000121000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000101691327685883729846210000103036830418304063035930133

Test 3: Latency 1->3

Code:

  sqdmulh v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000072071011611296340100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225009612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000084071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000048071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000078071011611296340100001003003830038300383003830180
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000147071011611296980100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000009071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000084071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000096071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000096071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5e696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010003006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010002706402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010001806402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010002106402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010002706402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010007806402162229630010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100015006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100017406402162229630010000103003830038300383003830038
10024300372250612954825100101010000101014950427731303001830037300372828732876710010201000020200003003730037111002110910101000010002706402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqdmulh v0.8h, v8.8h, v9.8h
  sqdmulh v1.8h, v8.8h, v9.8h
  sqdmulh v2.8h, v8.8h, v9.8h
  sqdmulh v3.8h, v8.8h, v9.8h
  sqdmulh v4.8h, v8.8h, v9.8h
  sqdmulh v5.8h, v8.8h, v9.8h
  sqdmulh v6.8h, v8.8h, v9.8h
  sqdmulh v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500008325801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051103162220036800001002004020040200402004020040
80204200391500008325801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001001051102162220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040
80204200391500008325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001001051102162220036800001002004020040200402004020040
802042003915000016925801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040
8020420039150001086425801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040
802042003915000080325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001001051102162220036800001002004020040200402004020040
802042003915000028425801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051102162220036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500028725800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050205160532003680000102004020040200402004020040
8002420112150006125800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000101050206161532003680000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050205160532003680000102004020040200402004020040
80024200391500010325800101080000128000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050205160532003680000102004020040200402004020040
80024200391500048325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000102350205160532003680000102004020040200402004020040
80024200391500010325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050203160552003680000102004020040200402004020040
80024200391500014525800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050203160552003680000102004020040200402004020040
80024200391500014525800101080080108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050203160552003680000102004020040200402004020040
8002420039150004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050203160452003680000102004020040200402004020040
80024200391500010325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050204160532003680000102004020040200402004020040