Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMULL (scalar, D)

Test 1: uops

Code:

  sqdmull d0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372361254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303723147254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372361254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372361254825100010001000398313301830373037241532895100010002000303730371110011000003373116112630100030383038303830383038
1004303723147254849100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303723499254825100010001000398313301830853037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303722519254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303723452254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372361254825100010001000398313301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372261254825100010001000398313301830853037241532895100010002000303730371110011000000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqdmull d0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372251061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)090f18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225002000027029548251001010100001010000504277313030018300853003728287328767100102010000202000030037300371110021109101010000100000006403162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006403162229630010000103003830038300383003830038
100243003722500000009329548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000606403162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006403162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402163329630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqdmull d0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282658287631010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000384929548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313300183003730037282653287451010020010000200201143003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020213303008530037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037224000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000001640216222963010000103003830038300383003830038
1002430037224000612954825100171010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037224000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037224000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqdmull d0, s8, s9
  sqdmull d1, s8, s9
  sqdmull d2, s8, s9
  sqdmull d3, s8, s9
  sqdmull d4, s8, s9
  sqdmull d5, s8, s9
  sqdmull d6, s8, s9
  sqdmull d7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100801165006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150341258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9abacbranch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000030502001016121220036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001516151120036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001516161320036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001116161320036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001316141520036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001816161420036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001316131320036080000102004020040200402004020040
800242003915000000000002732580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001016121720036080000102004020040200402004020040
80024200391500000000000402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001516121520036080000102004020040200402004020040
80024200391500000000000612580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100000000502001516131020036080000102004020040200402004020040