Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMULL (vector, 2D)

Test 1: uops

Code:

  sqdmull v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300006125482510001000100039831330183037303724153289510001000200030373037111001100010373116112630100030383038303830383038
10043037230000822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230000612548251000100010003983133018303730372415328951000100020003037303711100110006373116112630100030383038303830383038
10043037220000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037231000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230030612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqdmull v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100102100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100010507101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313300180300373003728265328763101002001016520020000300373003711102011009910010010000100067827101161129634100001003003830038300383003830038
1020430037225061295484510128109100001001000050042786703001803003730084282653287451027420010165200200003008530085211020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001833003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003013330038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723306129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282872528767100102010000202000030084300371110021109101010000100640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383022730038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722508929548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225014729548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqdmull v0.2d, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250014529548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
10204300372250016629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038
1020430037241006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100071011601129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010149604277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038
100243003723696129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640316332963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqdmull v0.2d, v8.2s, v9.2s
  sqdmull v1.2d, v8.2s, v9.2s
  sqdmull v2.2d, v8.2s, v9.2s
  sqdmull v3.2d, v8.2s, v9.2s
  sqdmull v4.2d, v8.2s, v9.2s
  sqdmull v5.2d, v8.2s, v9.2s
  sqdmull v6.2d, v8.2s, v9.2s
  sqdmull v7.2d, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150150412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000030511041611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200770800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
8020420039150004212580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500178258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100050200061600224200360080000102004020040200402004020040
8002420039150040258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100050200041600042200360080000102004020040200402004020040
8002420039150040258001010800001080000506400000520020200392003999963100198001020800002016000020039200391180021109101080000100050205121600124200360080000102004020040202462004020040
8002420039149040258001010800001080000506400000520020200392003999963100198001020800002016000020039200392180021109101080000100050200021600042200360080000102004020040200402004020040
8002420039150040258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100050200041600124200360080000102004020040200402004020040
8002420039150040258001010800001080000506400001020020200392003999963100198001020800002016000020039200391180021109101080000100050200041600072200360080000102004020040200402004020040
8002420039155040258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000102050200041600026200360080000102004020040200402004020040
80024200391500937258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100050200021600242200360080000102004020040200402004020040
8002420039150040258001010800001080000506400000520020200392003999963100198001020800002016000020039200391180021109101080000100050205241600144200360080000102004020040200402004020040
8002420039150040258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100050460041600144200360080000102004020040200402004020040