Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQNEG (vector, 2D)

Test 1: uops

Code:

  sqneg v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001100073116112629100030383038303830863038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqneg v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372240000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000906129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011613296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043007422611430025129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000006129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006403162229629110000103003830038300383003830038
10024300372240000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372240000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000612953825100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010016402162229629010000103003830038300383003830038
100243003722500007262954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500007262954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500007262954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500001562954725100101010000101014850427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqneg v0.2d, v8.2d
  sqneg v1.2d, v8.2d
  sqneg v2.2d, v8.2d
  sqneg v3.2d, v8.2d
  sqneg v4.2d, v8.2d
  sqneg v5.2d, v8.2d
  sqneg v6.2d, v8.2d
  sqneg v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000001001115118016020036800001002004020040200402004020040
802042003915030818010810080008100800205006409442002020039200399977699908012020080032200800322003920103118020110099100100800001000000001115118016020036800001002004020040200402004020040
80204200391504801258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000211143021115135016020246800001002004020040200402009020040
8020420039150302580108100800081008002050064013220020200392003999861299908012020080032200800322003920039118020110099100100800001004001141301115173128020036800001002004020040200402004020040
802042003915030798021210080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040
802042003915051258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9e9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800000100000502018168172003680000102004020040200402004020040
80024200391500000021225800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800000100000502061617152003680000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000010000050207161582003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800000100000502014161762003680000102004020040200402004020040
800242003915000000727258001010800801080000506400001200202003920039999631001980010208000020800002003920039118002110910108000001000005020141617172003680000102004020040200402004020040
8002420039150000002302580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000010000050206161772003680000102004020040200402004020040
8002420039150000001052580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000010000050208166172003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800000100000502014161782003680000102004020040200402004020040
80024200391500000040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000001000005020161617172003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800000100000502012161762003680000102004020040200402004020040