Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMLAH (by element, 4S)

Test 1: uops

Code:

  sqrdmlah v0.4s, v1.4s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722006125482510001000100039831303018303730372415328951000100030003037303711100110005073216112630100030383038303830383038
1004303723196125482510001000100039831303018303730372415328951000100030003037303711100110000373116112630100030383038303830383038
1004303723006125482510001000100039831303054303730372415328951000100030003037303711100110000373116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100030003037303711100110001073216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372301261254825100010001000398313030183037303724153289510001000300030373037111001100006973116222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110003073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqrdmlah v0.4s, v1.4s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000842954825101001001000010010000500427731303001830037300372826503287451010020010000200300003003730037111020110099100100100001000220371212162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100010071212163229634100001003003830038300383003830038
102043003722500210768295482510100100100001001000050042800270300183003730037282650328764101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300543003730037282650328745101002001000020030000300373003711102011009910010010000100030071012162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282930328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000061295486410100100100001001000050042773130300183003730037282650328745101002001000020030000300373003711102011009910010010000100010371612162229670100001003003830086300383003830038
102043003722510171061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100022371012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001028300640416332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000101000640316332963010000103003830038300383003830038
1002430179224006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000101000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225606129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000101000640316332963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
100243003722500100429548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830180
1002430037224006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225306129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316332963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqrdmlah v0.4s, v0.4s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225062429548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830086
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100067101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007100161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372331414146452883972954825100101010048171193750427731303001830037300372828732876710010201000020300003008430037111002110910101000010227706404162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010206402162229630010000103003830038300383022830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722500000612954825100101010008101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010036402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038301803003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqrdmlah v0.4s, v1.4s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250001702954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001872954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001892954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240001682954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001662954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500012429548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710116112963418100001003003830038300383003830038
10204300372250001682954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001032954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001662954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010002724071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403162229630010000103022730038300383003830038
10024300372250000000002512954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037224000000000612954825100101010000101000050427731303001830037300372828732876710010201018020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773130300183003730037282873287891001020100002030000300373003711100211091010100001000001015606402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103017830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah v0.4s, v8.4s, v9.s[1]
  movi v1.16b, 0
  sqrdmlah v1.4s, v8.4s, v9.s[1]
  movi v2.16b, 0
  sqrdmlah v2.4s, v8.4s, v9.s[1]
  movi v3.16b, 0
  sqrdmlah v3.4s, v8.4s, v9.s[1]
  movi v4.16b, 0
  sqrdmlah v4.4s, v8.4s, v9.s[1]
  movi v5.16b, 0
  sqrdmlah v5.4s, v8.4s, v9.s[1]
  movi v6.16b, 0
  sqrdmlah v6.4s, v8.4s, v9.s[1]
  movi v7.16b, 0
  sqrdmlah v7.4s, v8.4s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009015000211258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
160204200641500062258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
16020420064150001286258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002030720065200652006520065
160204200641500039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
1602042006415000144258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
1602042006415100102258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
160204200641500039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065
1602042006415000372258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420075150102087258001212800001280000626400001115200272004620046322800122080000202400002004620046111600211091010160000100001003718211120211111320043215160000102004720047200472004720047
16002420046150001645258001212800001280000626400001115200272004620046322800122080000202400002004620050111600211091010160000100001003818511120211151120043215160000102004720047200472004720047
16002420046150001851258001212800001280000626400001115200272004620046322800122080000202400002004620046111600211091010160000100001003618511120211111220043230160000102004720047200472004720047
1600242004615000144992580012128000012800006264000011152003120046200463228001220800002024000020046200501116002110910101600001000010033185192422191320043215160000102004720047200472004720047
16002420046150001345258001212800001280000626400001115200272004620046322800122080000202400002004620046111600211091010160000100001003418511020211131120043215160000102004720047200472004720051
160024200461500014154258001212800001280000626400001115200272004620046322800122080000202400002004620046111600211091010160000100001003518521120221121020043215160000102004720047200472005120051
16002420050150001512925800121280000128000062640000111520027200502005032280012208000020240000200462004611160021109101016000010000100341861920221111320043215160000102004720047200472004720051
16002420046150001412925800121280000128000062640000111520027200462004632280012208000020240000200462004611160021109101016000010000100361861112021111920043215160000102004720047200472004720047
160024200461500015452580012128000012800006264000011152002720046200461022800122080000202400002004620046111600211091010160000100001003318611020211111320043215160000102004720047200472004720047
16002420046150001545258001212800001280000626400001115200272004620046322800122080000202400002004620046111600211091010160000100001003318611320212101120043230160000102004720047200472004720047

Test 6: throughput

Count: 12

Code:

  sqrdmlah v0.4s, v12.4s, v13.s[1]
  sqrdmlah v1.4s, v12.4s, v13.s[1]
  sqrdmlah v2.4s, v12.4s, v13.s[1]
  sqrdmlah v3.4s, v12.4s, v13.s[1]
  sqrdmlah v4.4s, v12.4s, v13.s[1]
  sqrdmlah v5.4s, v12.4s, v13.s[1]
  sqrdmlah v6.4s, v12.4s, v13.s[1]
  sqrdmlah v7.4s, v12.4s, v13.s[1]
  sqrdmlah v8.4s, v12.4s, v13.s[1]
  sqrdmlah v9.4s, v12.4s, v13.s[1]
  sqrdmlah v10.4s, v12.4s, v13.s[1]
  sqrdmlah v11.4s, v12.4s, v13.s[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)0318191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1202043019822500000410251201001001200001001200005009900001300203004230039149733149971201002001200002003600003004130039111202011009910010012000010000000007610116123003601200001003004030040300773070130944
1202043004222500000410251201011001200001001200005009900001300203004230039149733150001201002001200002003600003004230039111202011009910010012000010000000007610116113003601200001003004030040300403004030040
1202043003922500000410251201001001200001001200005009600001300233003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040309443004030040
1202043004022500000440251201011001200001001200005009900001300203004230039149733150001201002001200002003600003004230039111202011009910010012000010000000007610116113003601200001003004030040300433004030043
1202043004122500001410251201001001200011001200005009600001300233003930039149733149971201002001200002003600003003930039111202011009910010012000010000010007610116113003601200001003004030040300433004030041
1202043003922500001410251201001001200011001200005009600001300233092230039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003801200001003004030040300403004030040
1202043003922500000610251201011001200001001200005009600001300203003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113174601200001003004030040300433004030043
1202043004122500000413489251201171001200011001200005009600001300203003930943149733149971201002001200002003600003003930943111202011009910010012000010000000007610116113003601200001003004030040300433004230043
12020430039225000007260251201001001200001001200005009600001300203004230039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003601200001003004030040300433004030944
1202043003922500000440251201001001200011001200005009600001300203004230039158503150001201002001200002003600003004230039111202011009910010012000010000000007610116113003601200001003004330040300403004330040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)19373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
120024307602250000015502512001010120000101200005096000001030020300393003914996315019120010201200002036000030039300391112002110910101200001000010753851516343005000120000103004030040300403015730040
12002430039225100052610251200101012000010120000501094524015300203003930093149961715020120010201200002036000030101300391112002110910101200001000000752054316443004900120000103004030040300403004030040
12002430039225000114102512001010120098101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000010752054316343004800120000103004030040300403004030040
120024300392250000092202512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000003752054316433004100120000103004030040300403004030040
1200243003922500000104002512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000003752050416343003600120000103004030040300403004030040
12002430039238000004470251200101012000010120000509600000153002030039300391499631590212001020120000203600003003930039211200211091010120000102200520752054316343003900120000103004031751300403010330040
120024300392250011010502512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000100752054316343174000120000103004030040300403004030040
12002430039225000018202512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000003752054416443004000120000103004030040300403004030040
12002430039225010006302512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000000752054316343174000120000103004030040300403004030040
120024300392250000012402512001010120000101200005096000001530020300393003914996315019120010201200002036000030039300391112002110910101200001000000752054316433003600120000103004030105300413004030040