Firestorm: SQRDMLAH (by element, 8H) measurements

Code:

  sqrdmlah v0.8h, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	251	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	88	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	12	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	6	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	6	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	6	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	250	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrdmlah v0.8h, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	710	1	2	16	2	2	29634	2	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	7	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	3	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	1	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	1	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	25	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	3	16	2	2	29634	1	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	3	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	631	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrdmlah v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	12	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10166	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	12	710	1	16	1	1	29668	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	12	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	12	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	12	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	631	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	18	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	6	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	9	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10255	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30495	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	12	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	8	3	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	15	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	18	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	614	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29702	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29702	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqrdmlah v0.8h, v1.8h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30084	225	6	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	621	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	18	105	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	5	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	54	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30229	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	9	0	1104	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	564	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	635	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah v0.8h, v8.8h, v9.h[1]
  movi v1.16b, 0
  sqrdmlah v1.8h, v8.8h, v9.h[1]
  movi v2.16b, 0
  sqrdmlah v2.8h, v8.8h, v9.h[1]
  movi v3.16b, 0
  sqrdmlah v3.8h, v8.8h, v9.h[1]
  movi v4.16b, 0
  sqrdmlah v4.8h, v8.8h, v9.h[1]
  movi v5.16b, 0
  sqrdmlah v5.8h, v8.8h, v9.h[1]
  movi v6.16b, 0
  sqrdmlah v6.8h, v8.8h, v9.h[1]
  movi v7.16b, 0
  sqrdmlah v7.8h, v8.8h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	151	0	0	83	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	2	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80315	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	666	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	29	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	60	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	52	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	81	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	3	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10111	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20072	150	21	322	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	0	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	34	0	10027	3	1	1	6	24	2	1	1	6	6	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	51	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	7	20	2	1	1	6	4	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	66	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10026	3	1	1	4	20	2	1	1	6	6	20043	2	30	0	160000	10	20051	20051	20051	20051	20051
160024	20046	150	0	72	25	80012	12	80000	12	80000	62	640000	0	1	20027	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	3	20	2	1	1	4	4	20043	2	30	0	160000	10	20047	20051	20051	20051	20051
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	0	1	20031	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	10032	3	2	1	4	20	2	1	1	3	4	20047	2	30	0	160000	10	20051	20051	20051	20051	20047
160024	20050	150	0	72	25	80012	12	80000	12	80000	62	640000	1	1	20031	20046	20046	0	3	22	80012	20	80000	20	240000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	12	10030	3	1	1	7	24	4	2	2	5	4	20043	2	15	0	160000	10	20047	20047	20051	20047	20047
160024	20050	150	0	51	25	80012	12	80208	12	80000	62	640000	0	1	20031	20050	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	2	6	24	4	1	1	7	6	20047	2	30	0	160000	10	20047	20051	20051	20051	20047
160024	20046	150	0	51	25	80012	12	80000	12	80000	62	640000	1	1	20027	20050	20046	0	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10026	3	2	2	4	20	4	2	2	4	4	20043	2	30	0	160000	10	20047	20047	20047	20051	20047
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	0	1	20031	20050	20050	0	3	22	80012	20	80000	20	240000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	10033	6	2	1	8	24	4	2	1	4	4	20043	2	30	0	160000	10	20047	20047	20051	20051	20051
160024	20050	150	0	51	25	80012	12	80000	12	80000	62	640000	0	1	20031	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10029	3	1	2	3	24	4	2	2	3	4	20043	2	15	0	160000	10	20047	20047	20047	20047	20047

Test 6: throughput

Count: 12

Code:

  sqrdmlah v0.8h, v12.8h, v13.h[1]
  sqrdmlah v1.8h, v12.8h, v13.h[1]
  sqrdmlah v2.8h, v12.8h, v13.h[1]
  sqrdmlah v3.8h, v12.8h, v13.h[1]
  sqrdmlah v4.8h, v12.8h, v13.h[1]
  sqrdmlah v5.8h, v12.8h, v13.h[1]
  sqrdmlah v6.8h, v12.8h, v13.h[1]
  sqrdmlah v7.8h, v12.8h, v13.h[1]
  sqrdmlah v8.8h, v12.8h, v13.h[1]
  sqrdmlah v9.8h, v12.8h, v13.h[1]
  sqrdmlah v10.8h, v12.8h, v13.h[1]
  sqrdmlah v11.8h, v12.8h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30843	231	0	0	0	0	0	0	18	171	0	25	120152	100	120052	100	120000	500	960000	0	30020	30039	30039	15857	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30040	30040	30040
120204	30103	225	0	0	0	0	0	0	0	751	3523	25	120100	100	120000	100	120000	500	960000	1	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30951	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30923	30040	30952
120204	30039	225	0	0	0	0	0	0	0	768	0	25	120100	100	120000	100	120000	500	960000	1	30020	30039	30039	15857	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30952	30040	30040
120204	30039	225	0	0	0	0	0	0	0	104	0	25	120100	100	120000	100	120000	500	960000	0	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30952	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	0	790	0	25	120100	100	120000	100	120000	500	960000	1	30020	30039	30951	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30948	0	120000	100	30040	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	0	83	0	25	120100	100	120000	100	120000	500	960000	1	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	0	811	0	25	120100	100	120000	100	120000	500	960000	1	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30952	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	0	61	0	25	120100	100	120000	100	120000	500	960000	1	30932	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30040	30040	30040
120204	30039	225	0	0	0	0	0	0	17	104	0	25	120100	100	120052	100	120000	500	960000	1	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	1	0	0	7610	2	16	2	2	30036	0	120000	100	30040	30040	30040	30040	30040
120204	30039	224	0	0	0	0	0	0	36	41	0	25	120100	100	120000	100	120000	500	960000	0	30020	30039	30951	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	30036	0	120000	100	30952	30040	30040	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30040	227	0	0	0	0	88	3405	25	120010	10	120052	10	120000	50	4394061	1	1	30021	30040	30040	14996	3	15019	120010	20	120000	20	360000	31750	30040	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	3	1	1	14	16	2	1	1	6	4	31747	0	30	5	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	69	0	25	120011	10	120000	10	120000	50	990000	1	1	30020	30039	30039	16677	3	16730	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	3	2	2	4	16	2	2	2	6	4	30036	0	15	5	120000	10	30040	30040	30040	30040	30040
120024	30922	225	0	0	17	0	475	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7524	3	1	1	6	16	2	1	1	6	4	30037	0	15	5	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	113	0	25	120010	10	120000	10	120000	50	960000	1	1	30021	30040	30039	15850	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	2	0	0	0	7522	3	1	2	11	16	2	1	2	10	6	30036	0	15	5	120000	10	30041	31751	31751	30040	30040
120024	30922	225	0	0	0	0	674	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	3	1	1	10	16	4	1	1	4	10	30036	0	15	5	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	824	3405	25	120028	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	3	15902	120010	20	120000	20	360000	30039	30040	1	1	120021	10	9	10	10	120000	10	0	0	0	1	0	0	7522	6	2	1	10	16	4	1	1	10	10	30036	0	15	5	120000	10	30040	30923	30040	30040	30040
120024	30039	225	0	0	0	0	67	9988	25	120011	10	120000	10	120000	50	4394061	1	1	31731	30040	30039	14996	3	15019	120010	20	120000	20	360000	30039	30040	1	1	120021	10	9	10	10	120000	10	0	0	0	1	0	0	7524	3	1	2	10	16	2	3	1	5	6	30036	0	15	10	120000	10	30923	30040	30923	30040	30040
120024	30040	225	0	0	1	0	329	0	25	120010	10	120000	10	120000	50	4283400	1	1	30932	30039	30039	14996	3	15019	120010	20	120000	20	360000	30922	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	3	2	1	6	16	2	1	1	4	10	30036	2	15	10	120000	10	30040	30040	30041	30041	30040
120024	30042	225	0	0	0	0	69	0	25	120011	10	120017	10	120000	50	990000	1	1	30021	30040	30039	14996	3	15019	120010	20	120000	20	360000	31750	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	4	6	30037	0	15	5	120000	10	30041	30040	30040	30040	30040
120024	30040	225	0	0	0	0	75	0	25	120010	10	120000	10	120000	50	960000	1	1	30903	30039	30922	14996	3	15020	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7524	3	1	1	10	16	2	1	1	4	6	31747	0	30	5	120000	10	30040	30040	30040	30040	30040

SQRDMLAH (by element, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations