Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMLAH (scalar, H)

Test 1: uops

Code:

  sqrdmlah h0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125482510001000100039831330183037303724153289510001000300030373037111001100000073216122630100030383038303830383038
10043037220006125482510001000100039831330183037303724153289510001000300030373037111001100000373116122630100030383038303830383038
100430372200017025482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
10043037220006125482510001000100039831330183037303724153289510001000300030373037111001100000673116212630100030383038303830383038
1004303723017406125482510001000100039831330183037303724153289510001000300030373037111001100000673216222630100030383038303830383038
10043037230006125482510001000100039831330183037303724153289510001000300030373037111001100000073216122630100030383038303830383038
10043037220129025125482510001000100039831330183037303724153289510001000300030373037111001100000073116222630100030383038303830383038
10043037230006125482510001000100039831330183037303724153289510001000300030373037111001100000073116112630100030383038303830383038
10043037220006125482510001000100039831330183037303724153289510001000300030373037111001100000073216112630100030383038303830383038
10043037230006125482510001000100039831330183037303724153289510001000300030373037111001100000073116222630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqrdmlah h0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204301802320063336006129548251010010610000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000000010329548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100010071012162229634100001003003830038300383003830038
1020430037225000000012429548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100003071012162229634100001003003830038300383003830038
10204300372250000150069129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100010071012162229634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
10204300372250000156006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038
1020430037225000030006129548251010010010000100100005004277313130018300373003728272328745101002001000020030000300373003711102011009910010010000100000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722556761295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722537861295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
1002430037225414146295482510010101000010100005042773133001830037300372828732876710608201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722449861295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722533961295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372253103295482510010101000010100005042773133001830037300372828732876710010201000020300003003730084311002110910101000010000661324432963010000103022630038300383003830038
10024300372251261295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010020640316332963010000103003830038300383008430038
100243003722528861295482510010101000010100005042773133001830037300372828732876710310201000020300003003730037111002110910101000010003640316332963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710159201000020300003003730037111002110910101000010000640416332963010000103003830038300383003830038
10024300372250346295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010013640316332963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqrdmlah h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372259612954825101001001000010010000500427731313001830037300372826516287451010020010000200300003003730037111020110099100100100001000007102161129634100001003003830038300383003830038
102043003722534582295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722561899295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037224661295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037224661295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225361295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
10204300372253961295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372252161295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225661295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372257806129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372253606129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001010640316332963010000103003830038300383003830038
10024300372252706129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372251806129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372253906129548251001010100001010000504277313300183003730037282873287671046020100002030000300373003711100211091010100001000640316432966810000103003830038300383003830038
100243003722530906129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372255706129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722560072629548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372244506129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372253606129548251001010100001010000504277313300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  sqrdmlah h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000390061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000000001710116112963400100001003003830038300383003830038
102043003722500000600216295482510100100100001001000050042773133001830037302282826532874510100200100002003000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773133001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000710116112963410100001003003830038300383003830038
102043003722500000000757295482510100100100001201000050042773133001830084300372826532874510100200100002003000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830135
1020430037233000103688061295482510113100100081001000050042773133003630037300372826532874510100200101652123149430177300371110201100991001001000010000010000732116112963400100001003003830038300383003830038
1020430037233000103900822947625101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100200103007101145112963400100001003021630181301823018130134
102043017823400000133800822954825101001051000015610000500427731330018300373008428265328745101002001000020430000300373003711102011009910010010000100043102785800780141113006300100001003003830075305173003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722596129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372243096129548251001010100001010000504277313130054300833013228287328767100102010000203000030037300373110021109101010000100020640216232963010000103003830038300863003830038
10024300372253066129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225306129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372253156129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372255114729548441001010100001010298504277313030018300843003728287328767101602010000203000030037300371110021109101010000103102795640516422963010000103003830038300383003830038
1002430037225636129548251001010100001010000504277313130018300373003728287328843100102010000203000030037300371110021109101010000100100640216222963010000103003830038300383003830038
1002430037225668229548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722427310329548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225156129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah h0, h8, h9
  movi v1.16b, 0
  sqrdmlah h1, h8, h9
  movi v2.16b, 0
  sqrdmlah h2, h8, h9
  movi v3.16b, 0
  sqrdmlah h3, h8, h9
  movi v4.16b, 0
  sqrdmlah h4, h8, h9
  movi v5.16b, 0
  sqrdmlah h5, h8, h9
  movi v6.16b, 0
  sqrdmlah h6, h8, h9
  movi v7.16b, 0
  sqrdmlah h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200901500000540392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
16020420064150000000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
16020420064150000000392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
16020420064150000000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
160204200641500000540392580100100800001008000050064000000200452006420064322801002008000020024125120064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
16020420064150000000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
16020420064150000000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
1602042006415000003303925801001008000010080000500640000012004520064200643228010020080000200240000200642006411160201100991001001600001000000001011221622200610451600001002006520065200652006520065
16020420064151000000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065
160204200641510000603925801001008000010080000500640000012004520064200643108801002008000020024000020064200641116020110099100100160000100000000101122162220061001600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420053150154502580012128000012800006264000000202642005020052032280012208000020240000200502005211160021109101016000010010035622122432291220049231160000102005320051200512005120051
16002420050151125102580012128000012800006264000000202212005220052032280012208000020240000200522005211160021109101016000010010035622824422101020047230160000102005120051200512004720047
16002420046150245102580012128000012800006264000000202602005220046032280012208000020240000200502005011160021109101016000010010033622112441111920047215160000102005320051200512005120047
1600242004615035102580012128000012800006264000000201962005020050036480012208000020240000200502005011160021109101016000010010037622926422121220047230160000102005320053200512005320051
1600242005015024510258001212800001280000626400000120201200522005003228001220800002024000020050200501116002110910101600001001003762292532112920049230160000102005120051200512005120053
16002420052150125102580012128000012800006264000010202002004620052032280012208000020240000200502005011160021109101016000010010032622102632281020049230160000102004720051200472005120047
16002420046150245121092258001212800001280000626400000020214200462005203228001220800002024000020052200501116002110910101600001001003562292441291020049231160000102005120047200532005320053
16002420052150051025800121280000128000062640000012021320052200520322800122080000202400002005020050111600211091010160000100100376211124222121220047230160000102005320051200512005120053
160024200521501545025800121280000128000062640000102021520050200500322800122080000202400002005220050111600211091010160000100100366221226422101120047230160000102005120051200532005320053
160024200501501545025800121280000128000062640000012019920052200520322800122080000202400002005220050111600211091010160000100100366221020412111120043215160000102005320047200532004720053

Test 6: throughput

Count: 16

Code:

  sqrdmlah h0, h16, h17
  sqrdmlah h1, h16, h17
  sqrdmlah h2, h16, h17
  sqrdmlah h3, h16, h17
  sqrdmlah h4, h16, h17
  sqrdmlah h5, h16, h17
  sqrdmlah h6, h16, h17
  sqrdmlah h7, h16, h17
  sqrdmlah h8, h16, h17
  sqrdmlah h9, h16, h17
  sqrdmlah h10, h16, h17
  sqrdmlah h11, h16, h17
  sqrdmlah h12, h16, h17
  sqrdmlah h13, h16, h17
  sqrdmlah h14, h16, h17
  sqrdmlah h15, h16, h17
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)1e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044004030001814125160100100160000100160000500128000000400204004940039199733199971601002001600002004800004004940049111602011009910010016000010000000010110116114003601600001004004040050400404004940050
1602044003930000185125160100100160017100160000500131999901400304003940039199733199971601002001600002004800004004940039111602011009910010016000010000000010110116114004601600001004005040040400404004040050
160204400393000005125160100100160000100160000500243886500400204003940039199733200061601002001600002004800004004940049111602011009910010016000010000000010110116114003601600001004004040040400404004040040
160204400393000005125160117100160000100160000500128000001400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004004040049400504004040049
160204400392990004125160100100160000100160000500128000010400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000000110110116114003601600001004004040040400494004040050
160204400392990004125160100100160018100160000500239908201400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004004040040400404004040040
160204400393000004125160118100160000100160000500128000001400204003940040199733199971601002001600002004800004003940039111602011009910010016000010000000010110116114003601600001004005040050400404004940049
160204400483000004125160117100160000100160000500243886501400204003940039199733200071601002001600002004800004003940039111602011009910010016000010000000010110116114004601600001004005040050400504004040040
160204400483000004125160118100160000100160000500132000000400204003940040199733200071601002001600002004800004003940039111602011009910010016000010000000010110116114004501600001004004940040400404004040040
160204400393000004125160118100160000100160000500128000000400204003940049199733199971601002001600002004800004004040048111602011009910010016000010000000010110116114003601600001004004040040400404005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss instruction (0a)1e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244004830001000521025160010101600001016000050128000011540020400394003919996320019160010201600002048000040048400391116002110910101600001000100228115162115540036206160000104004040040400404004040040
16002440039300000005202516001010160000101600005012800000154002940048400391999632001916001020160000204800004003940039111600211091010160000100010022115251642244400454012160000104004040040400404004040041
16002440048300000005202516001010160017101600005023989990154002040039400391999632001916001020160000204800004003940071111600211091010160000100010024115221642254400464012160000104004040040400414004140049
16002440039300000006102516001010160000101600005023990550154003040039400391999632002816001020160000204800004003940039311600211091010160000100010024115241642223400454012160000104004940040400494004040049
160024400392990000052025160010101600001016000050239899901540020400394004819996320019160010201600002048000040039400391116002110910101600001052010024115251642255400454012160000104004040040400404007240040
1600244003930000001724202516002710160000101600005012800000154002040039400391999632001916001020160000204800004004940039111600211091010160000100010024115251641253400684012160000104004040040400404004040041
16002440039300000061520251600101016000010160000501320000105400204003940039199963200191600102016000020480000400394003911160021109101016000010001002462231642234400364018160000104004940040400494004940040
1600244003930000000520251600711016006110160000502398999015400204003940039199963200191600102016000020480000400394003911160021109101016000010001002462241642255400364012160000104004040040400404004040040
16002440039300000015202516001010160000101600005023989991154002040039400391999632001916001020160000204800004003940039111600211091010160000100010022112241642244400364012160000104004040040400404005040040
16002440048300000015202516001010160000101600005012800001154002040039400391999632001916001020160000204800004003940039111600211091010160000100010024115241642244400364012160000104004040040400404004040040