Firestorm: SQRDMLAH (vector, 4S) measurements

Code:

  sqrdmlah v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	0	0	0	103	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	9	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	103	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	79	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	3	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrdmlah v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	3	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	712	0	2	16	2	2	29634	0	10000	100	30038	30086	30038	30038	30038
10204	30037	225	0	0	0	0	15	0	0	61	29548	25	10100	100	10000	100	10000	511	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10497	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28762	10100	200	10000	200	30492	30037	30037	3	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30086
10204	30037	225	0	0	0	0	3	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	3	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10112	100	10000	100	10149	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30495	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	710	0	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4278675	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	755	0	2	40	2	2	29634	4	10000	100	30038	30038	30135	30086	30180

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	3	16	3	3	29630	10000	10	30038	30081	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	640	3	16	4	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	4	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	536	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrdmlah v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	0	253	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10180	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	204	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	57	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	297	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	243	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	226	0	0	0	330	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30162	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	2	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	15	61	29548	25	10010	12	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30227	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	1	10000	10	30038	30038	30206	30038	30038
10024	30037	225	0	0	4	0	61	29548	25	10029	12	10000	12	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	8455	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30972	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	417	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30084	30085	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	60	4277313	1	30018	30037	30037	28287	21	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30084	225	0	0	0	459	103	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30085	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	6	0	640	2	16	2	2	29630	0	10000	10	30038	30134	30038	30038	30038
10024	30037	225	1	1	0	552	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqrdmlah v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	105	0	0	61	29548	25	10100	100	10000	100	10148	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	21	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	45	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	51	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29691	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28278	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	61	29548	25	10100	100	10008	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	12	0	0	61	29548	25	10100	100	10000	100	10148	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	42	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	21	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	174	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	21	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30084	30037	28287	3	28767	10010	20	10162	20	30486	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	11	16	10	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	6	0	644	8	16	11	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	450	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28836	10010	20	10000	20	30000	30037	30084	3	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	5	48	10	10	29666	0	10000	10	30038	30038	30134	30216	30038
10024	30037	226	0	0	552	2	66	29548	44	10010	12	10000	10	10000	50	4277313	30126	30037	30037	28287	3	28767	10010	20	10330	22	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	10	16	11	11	29630	0	10000	10	30178	30038	30038	30038	30038
10024	30085	225	0	0	0	2	66	29512	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2848	0	644	10	16	10	15	29630	0	10000	10	30132	30038	30038	30038	30038
10024	30037	225	0	0	0	2	66	29548	25	10010	14	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10310	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	4	0	0	0	0	0	0	644	10	16	10	10	29774	0	10000	10	30038	30038	30038	30038	30225
10024	30037	225	0	0	0	2	66	29512	25	10010	10	10000	10	10596	50	4277313	30126	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	10	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28293	3	28767	10010	20	10000	20	31956	30037	30178	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	0	0	644	11	16	10	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	543	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	4	1	10021	10	9	10	10	10000	10	0	0	0	0	2	3	0	644	11	16	11	12	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	2	66	29548	25	10010	10	10008	12	10149	50	4277313	30018	30037	30037	28287	3	28911	10609	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	644	10	16	5	10	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sqrdmlah v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sqrdmlah v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sqrdmlah v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sqrdmlah v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sqrdmlah v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sqrdmlah v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sqrdmlah v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20078	150	33	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	42	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	12	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80207	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	15	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	21	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	3	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	9	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	21	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	2	16	2	2	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d1	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20072	150	0	0	0	0	0	0	3	0	45	25	80012	12	80000	12	80000	68	640000	1	1	20031	20046	20052	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10036	6	0	2	2	9	20	4	1	1	11	11	20043	2	30	0	160000	10	20053	20053	20053	20051	20051
160024	20050	150	0	0	0	0	0	0	9	0	51	25	80012	12	80000	12	80000	62	640000	0	0	20031	20050	20052	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10032	3	0	1	1	9	20	2	1	1	11	12	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20093	150	0	0	0	0	0	0	3	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10034	3	0	1	1	9	20	2	1	1	10	11	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	0	303	0	615	25	80012	12	80000	12	80000	62	640000	1	1	20027	20050	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10037	3	0	1	1	9	20	2	1	1	9	9	20043	2	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	0	12	0	66	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10035	6	0	2	2	11	24	4	2	2	12	12	20047	2	30	0	160000	10	20051	20051	20053	20053	20053
160024	20050	150	0	0	0	0	0	0	45	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10036	6	0	2	2	12	26	4	2	2	10	10	20049	2	31	0	160000	10	20051	20053	20053	20051	20051
160024	20052	150	0	0	0	0	0	0	219	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10035	3	0	1	1	9	20	2	1	1	8	9	20043	2	15	0	160000	10	20047	20136	20047	20047	20047
160024	20050	150	0	0	0	0	0	0	9	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10035	6	0	2	2	8	24	3	2	2	9	9	20047	2	30	0	160000	10	20051	20051	20051	20053	20051
160024	20050	151	0	0	0	0	0	0	21	0	615	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20050	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	15	0	10036	6	0	2	2	10	24	3	2	2	12	12	20047	2	30	0	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	0	51	25	80012	12	80000	12	80000	62	640000	0	1	20033	20050	20050	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10032	3	0	1	1	11	20	2	1	1	11	10	20043	2	15	0	160000	10	20047	20047	20047	20047	20047

Test 6: throughput

Count: 16

Code:

  sqrdmlah v0.4s, v16.4s, v17.4s
  sqrdmlah v1.4s, v16.4s, v17.4s
  sqrdmlah v2.4s, v16.4s, v17.4s
  sqrdmlah v3.4s, v16.4s, v17.4s
  sqrdmlah v4.4s, v16.4s, v17.4s
  sqrdmlah v5.4s, v16.4s, v17.4s
  sqrdmlah v6.4s, v16.4s, v17.4s
  sqrdmlah v7.4s, v16.4s, v17.4s
  sqrdmlah v8.4s, v16.4s, v17.4s
  sqrdmlah v9.4s, v16.4s, v17.4s
  sqrdmlah v10.4s, v16.4s, v17.4s
  sqrdmlah v11.4s, v16.4s, v17.4s
  sqrdmlah v12.4s, v16.4s, v17.4s
  sqrdmlah v13.4s, v16.4s, v17.4s
  sqrdmlah v14.4s, v16.4s, v17.4s
  sqrdmlah v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40040	299	0	0	0	0	51	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	1	40029	40049	40039	19973	0	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40041	40040	40050	40049	40040
160204	40039	300	0	0	0	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	1	40020	40048	40039	19973	0	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40046	0	160000	100	40050	40040	40040	40050	40040
160204	40049	300	0	0	0	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1319999	0	40020	40049	40048	19973	0	3	20006	160100	200	160000	200	480000	40089	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40040	40040	40050	40049	40040
160204	40039	299	0	0	0	0	0	0	0	41	0	25	160100	100	160017	100	160000	500	1280000	1	40020	40039	40040	19973	0	3	19997	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40036	0	160000	100	40040	40040	40050	40049	40049
160204	40039	300	0	0	0	1	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	0	40029	40049	40039	19973	0	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	10110	1	16	1	1	40036	0	160000	100	40040	40040	40050	40049	40040
160204	40039	300	0	0	0	0	0	0	0	41	0	25	160100	100	160017	100	160000	500	1280000	0	40029	40039	40039	19973	7	3	19997	160100	202	160000	200	480000	40039	40088	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40045	0	160000	100	40040	40040	40040	40050	40040
160204	40039	300	0	0	0	0	0	0	0	51	0	25	160100	100	160000	100	160000	500	2399027	1	40033	40049	40048	19973	0	3	19997	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40045	0	160000	100	40049	40040	40040	40049	40040
160204	40039	300	0	0	0	0	0	0	0	61	0	25	160100	100	160000	100	160000	500	2399027	0	40029	40049	40039	19973	0	3	20007	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40045	0	160000	100	40040	40040	40040	40041	40040
160204	40039	300	0	0	0	0	0	0	0	50	0	25	160117	100	160000	100	160000	500	2398999	0	40020	40048	40071	19973	0	3	20029	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	40046	0	160000	100	40040	40049	40040	40049	40040
160204	40039	300	0	0	0	0	264	0	0	105	0	25	160117	100	160000	100	160000	500	1280000	0	40030	40048	40103	19973	0	3	19997	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	0	0	0	0	10110	1	16	1	1	40046	0	160000	100	40049	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	37	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	1	0	0	1	58	25	160010	10	160000	10	160000	50	1280000	1	1	0	40030	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	5	1	47	16	1	1	1	18	26	40036	2	21	7	160000	10	40050	40040	40090	40040	40040
160024	40039	300	1	0	15	0	1	68	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	3	1	24	16	1	1	1	15	26	40036	0	21	7	160000	10	40040	40040	40040	40040	40050
160024	40039	300	1	1	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40030	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	4	1	28	16	1	1	1	26	26	40036	0	21	7	160000	10	40040	40040	40040	40040	40040
160024	40039	300	1	3	0	0	1	723	25	160010	10	160018	10	160112	50	2438865	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	3	1	160021	10	9	10	10	160000	10	0	4	2	12	0	0	0	0	10024	8	4	1	26	16	1	8	1	25	27	40045	0	21	7	160000	10	40050	40050	40040	40040	40040
160024	40039	300	0	1	0	17	0	47	25	160096	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	5	1	16	16	1	1	1	26	20	40036	0	21	7	160000	10	40050	40050	40040	40040	40040
160024	40039	300	1	1	0	0	0	58	25	160028	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40040	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	5	1	27	16	1	1	1	26	26	40036	0	21	7	160000	10	40040	40040	40040	40040	40040
160024	40039	300	1	1	0	0	1	153	25	160010	10	160018	10	160000	50	1280000	1	1	5	40020	40040	40048	20018	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	2	9	0	0	0	0	10024	8	5	1	27	27	1	1	1	26	27	40036	0	21	7	160000	10	40040	40040	40040	40040	40040
160024	40039	300	1	1	24	35	1	490	25	160028	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	8	5	1	26	16	1	1	1	27	21	40046	0	21	7	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	1	88	25	160010	10	160000	10	160000	50	2438865	1	1	5	40029	40039	40039	19996	0	3	20019	160010	20	160000	20	480420	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	3	0	0	0	0	10024	8	6	1	27	16	1	1	1	21	26	40036	0	21	7	160000	10	40040	40041	40040	40040	40040
160024	40039	300	1	1	0	0	1	58	25	160010	10	160000	10	160000	50	1280000	1	1	5	40023	40039	40049	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	1	25	16	1	1	1	14	28	40036	0	21	7	160000	10	40040	40040	40040	40040	40040

SQRDMLAH (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations