Firestorm: SQRDMLSH (by element, H) measurements

Code:

  sqrdmlsh h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	9e	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398526	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	2	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2914	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	3	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrdmlsh h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	204	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	29634	0	0	10000	100	30038	30071	30071	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	103	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	3	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	9	0	0	61	29529	44	10100	103	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	1790	0	0	731	1	2	16	2	2	29634	3	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	1055	29548	25	10018	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	8340	0	0	640	4	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	3	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	166	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	166	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	0	168	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	3	3	29630	0	10000	10	30038	30038	30038	30228	30038
10024	30037	224	0	0	0	0	124	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	145	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	15	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrdmlsh h0, h0, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	24	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	6	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30084	30084	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	378	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	423	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	324	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	363	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	24	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10148	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	3	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sqrdmlsh h0, h1, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	613	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30083
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	105	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30540	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	24	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	1	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30054	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	60	82	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlsh h0, h8, v9.h[1]
  movi v1.16b, 0
  sqrdmlsh h1, h8, v9.h[1]
  movi v2.16b, 0
  sqrdmlsh h2, h8, v9.h[1]
  movi v3.16b, 0
  sqrdmlsh h3, h8, v9.h[1]
  movi v4.16b, 0
  sqrdmlsh h4, h8, v9.h[1]
  movi v5.16b, 0
  sqrdmlsh h5, h8, v9.h[1]
  movi v6.16b, 0
  sqrdmlsh h6, h8, v9.h[1]
  movi v7.16b, 0
  sqrdmlsh h7, h8, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	0	17	44	80100	200	80313	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	135	0	10111	2	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	3	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	123	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	9	0	0	337	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	3	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	152	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	0	3	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	0	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	3	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	155	0	0	12	0	68	27	80012	12	80000	12	80000	62	640000	1	1	10	20032	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	37	12	10037	16	2	2	11	34	4	2	2	6	12	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	0	51	67	80012	12	80000	12	80000	62	640000	0	1	10	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	29	105	10032	16	9	2	6	34	4	2	2	6	11	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20052
160024	20051	150	0	0	0	0	45	78	80012	12	80000	12	80000	62	640000	0	1	10	20032	20060	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	29	9	10034	13	8	1	7	34	2	2	1	12	7	20057	2	40	0	2	160000	10	20061	20052	20061	20052	20052
160024	20051	150	0	0	0	0	45	64	80012	12	80000	12	80000	62	640000	1	1	10	20041	20060	20051	3	22	80012	20	80000	20	240000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	10034	13	7	1	11	25	2	1	1	12	12	20048	2	20	0	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	45	76	80012	12	80000	12	80000	62	640000	0	1	10	20041	20051	20060	39	22	80012	20	80000	20	240000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	10030	16	9	1	8	34	2	2	1	6	11	20048	2	40	0	2	160000	10	20052	20061	20052	20061	20052
160024	20060	150	0	0	0	0	45	76	80012	12	80000	12	80000	62	640000	1	1	0	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	10037	16	9	2	12	34	4	2	2	12	10	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20061
160024	20069	150	0	0	0	0	51	57	80012	12	80000	12	80000	62	640000	0	1	10	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	35	3	10038	16	9	2	7	34	4	2	2	8	12	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20070
160024	20060	150	0	0	0	0	51	60	80012	12	80000	12	80000	62	640000	0	1	10	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	29	3	10038	16	9	2	12	34	4	2	2	7	12	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20052
160024	20051	150	0	0	0	0	87	84	80012	12	80000	12	80000	62	640000	0	1	10	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	3	10034	16	9	2	8	34	4	2	2	14	8	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20052
160024	20060	150	0	0	12	0	51	75	80012	12	80000	12	80000	62	640000	0	1	10	20041	20060	20060	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	1	3	10039	16	9	2	12	34	4	2	2	7	13	20057	2	40	0	2	160000	10	20061	20061	20061	20061	20052

Test 6: throughput

Count: 12

Code:

  sqrdmlsh h0, h12, v13.h[1]
  sqrdmlsh h1, h12, v13.h[1]
  sqrdmlsh h2, h12, v13.h[1]
  sqrdmlsh h3, h12, v13.h[1]
  sqrdmlsh h4, h12, v13.h[1]
  sqrdmlsh h5, h12, v13.h[1]
  sqrdmlsh h6, h12, v13.h[1]
  sqrdmlsh h7, h12, v13.h[1]
  sqrdmlsh h8, h12, v13.h[1]
  sqrdmlsh h9, h12, v13.h[1]
  sqrdmlsh h10, h12, v13.h[1]
  sqrdmlsh h11, h12, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30113	231	0	0	41	0	25	120100	100	120001	100	120000	500	960000	0	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	3	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30040	30043
120204	30039	225	0	0	41	0	25	120100	100	120001	100	120000	500	960000	0	30924	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30042	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30043	30040
120204	30042	225	0	53	41	0	25	120101	100	120000	100	120000	500	4289539	0	30020	30039	30042	14973	3	14997	120100	200	120000	200	360000	30039	30943	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30041	30040	30040	30040	30040
120204	30039	225	0	1	41	3489	25	120100	100	120001	100	120000	500	4283622	0	30023	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30043	30040	30040	30944
120204	30039	225	0	1	41	0	25	120100	100	120001	100	120000	500	960000	0	30020	30042	30039	14973	3	15901	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30039	120000	100	30040	30040	30043	30040	30043
120204	30039	225	0	0	41	0	25	120100	100	120000	100	120000	500	960000	0	30020	30042	30039	14973	3	15000	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30042	30040	30040	30043
120204	30039	224	0	0	44	0	25	120100	100	120000	100	120000	500	960000	0	30020	30042	30039	14973	3	15000	120100	200	120000	200	360000	30042	30922	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30043	30040
120204	30042	225	0	0	61	0	25	120100	100	120053	100	120000	500	960000	1	30023	30039	30039	14973	3	14997	120100	200	120000	200	360000	30943	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30039	120000	100	30040	30040	30944	30040	30944
120204	30039	225	0	0	41	0	25	120100	100	120053	100	120000	500	990000	0	30924	30039	30039	14973	3	14997	120100	200	120000	200	360000	30042	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30702	30043
120204	30039	225	0	1	41	0	25	120100	100	120001	100	120000	500	960000	0	30023	30039	30039	14973	3	14997	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	30036	120000	100	30040	30040	30040	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30048	225	1	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	1	0	0	7522	3	1	1	8	16	2	1	1	5	5	30036	0	15	5	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30922	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	4	0	0	7522	3	1	1	7	16	2	1	1	8	8	30036	0	15	5	120000	10	30040	30040	30040	30041	30040
120024	30039	225	0	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	1	7524	6	2	2	5	16	4	2	2	5	5	30036	0	30	10	120000	10	30040	30040	30040	30040	30802
120024	30039	225	0	0	0	0	1	52	6695	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	2	0	0	7524	6	2	2	8	17	4	2	2	6	9	30036	0	30	10	120000	10	30040	30040	30040	31744	30040
120024	30039	225	0	0	0	0	0	115	0	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	8	6	0	7524	6	2	2	6	16	4	2	2	6	7	30036	0	31	10	120000	10	30040	30040	30040	30041	30040
120024	30039	225	0	0	0	0	0	52	0	25	120010	10	120000	10	120112	50	960000	0	1	30020	30198	30922	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	6	2	2	7	16	3	2	2	7	5	30036	0	30	10	120000	10	30040	30040	30040	30048	30040
120024	30039	225	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	2	0	0	7524	6	2	2	6	16	4	2	2	6	5	30036	0	30	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	52	0	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15022	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	8	0	0	7524	6	2	2	6	16	4	2	2	7	6	30036	0	30	10	120000	10	30040	30040	30040	30091	30040
120024	30039	224	0	0	0	0	0	52	0	25	120028	10	120000	10	120000	55	960000	0	1	30020	30039	30039	14996	0	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	4	0	0	7524	6	2	2	6	16	4	2	2	5	6	30036	0	31	10	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	0	0	0	52	6695	25	120010	10	120000	10	120000	50	960000	0	1	30020	30039	30039	14996	0	3	15022	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	6	2	2	8	16	4	2	2	6	6	30036	0	31	10	120000	10	30040	30040	30040	30043	30040

SQRDMLSH (by element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations