Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMULH (by element, 2S)

Test 1: uops

Code:

  sqrdmulh v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
1004303723027925482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722041325482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372414328951000100020003037303711100110000073116112630100030383038303830383038
100430372208225482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723048925482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723042025482510001000100039831303018303730372415328951000100020003037303711100110000073116112627100030383038303830383038
100430372325829925482510001000100039831303018303730372414328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqrdmulh v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250012612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250024612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100030710011611296340100001003008630038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250007262954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250005362954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250007262954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300853003728265328745101002001000020020000300373003711102011009910010010000100000735011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500662954825100101010000101000050427731313001830037300372828732876710010201000020209743003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020209843003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101014850427731313001830037300372828732876710010201000020200003003730037111002110910101000010020064021602229630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000064021602229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqrdmulh v0.2s, v1.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313030018300373007028265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313130018300373003728265732874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037225000098529548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037225041226129548251010010010000100100005004277313030018300373003728265032874510100204100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313030018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
1020430037225400042029548251010010010000100100005004277313130018300373003728265032874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251112223419213452953064100281410016121014972427731303005430085300852829072879810010201033120203923013130133311002110910101000010130640416222963010000103003830038300383003830038
100243003722500000120612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722400040840612954825100101010000101000050427731313001830037300372828732876710010201016820200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000000612954825100101010000101000060427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000030612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243007022500000007262954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010060640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqrdmulh v0.2s, v8.2s, v9.s[1]
  sqrdmulh v1.2s, v8.2s, v9.s[1]
  sqrdmulh v2.2s, v8.2s, v9.s[1]
  sqrdmulh v3.2s, v8.2s, v9.s[1]
  sqrdmulh v4.2s, v8.2s, v9.s[1]
  sqrdmulh v5.2s, v8.2s, v9.s[1]
  sqrdmulh v6.2s, v8.2s, v9.s[1]
  sqrdmulh v7.2s, v8.2s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000051102161120036800001002004020040200402004020040
802042003915001804125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000370051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000051101161120036800001002004020040200402004020040
80204200391500120412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020142200399973399978010020080000200160000200392003911802011009910010080000100200251101161320036800001002004020040200402004020040
8020420039150121911292580100100800001008000050064000012002020039200399973399978010020080000200160000200392008931802011009910010080000100003051101161120036800001002004020040200402004020040
80204200391500270412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100013051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000051101161120036800001002004020040200402004020040
8020420039150000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100013051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500810402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000005020181617620036080000102004020040200402004020040
8002420039150000402580010108000010800005064000051200202003920039999631001980010208000020160000200392003911800211091010800001000005020171617820036080000102004020040200402004020040
80024200391500004025800101080000108000050640000512002020039200399996310019800102080000201600002003920039118002110910108000010000050201716171720036080000102004020040200402004020040
8002420039150000402580010108000010800005064000041200202003920039999631001980010208000020160000200392003911800211091010800001000005020171661720036080000102004020040200402004020040
8002420039150000402580010108000010800006064000041200202003920039999631001980010208000020160000200392003911800211091010800001000005020171617820036080000102004020040200402004020040
8002420039150000402580010108000010800005064000051200202003920039999631001980010208000020160000200392003911800211091010800001000005020171617820036080000102004020040200402004020040
8002420039150000402580010108000010800005064000051200202003920039999631001980010208000020160000200392003911800211091010800001000005020171617820036080000102004020040200402004020040
800242003915000040258001010800001080000506400005120020200392003999963100198001020800002016000020039200391180021109101080000100000502061681720036080000102004020040200402004020040
8002420039150000402580010108000010800005064000041200202003920039999631001980010208000020160000200392003911800211091010800001000005020171681720036080000102004020040200402004020040
80024200391500210402580010108000010800005064000061200202003920039999631001980010208000020160000200392003911800211091010800001000005020171617820036080000102004020040200402004020040