Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMULH (vector, 4S)

Test 1: uops

Code:

  sqrdmulh v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073316112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110002073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116122665100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110001073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqrdmulh v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042827410300183003730037282727287401010020010008200200163003730037111020110099100100100001000011171801600296460100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282726287401010020010008200200163003730037111020110099100100100001000011171701600296470100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001001000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296342100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010048300071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001001000071011611296340100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000030006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
1002430037225000000726295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
1002430037225000000726295486310010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000030606402162229630010000103003830038300383003830038
100243003722500003061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954810010010101000010100005042773131300183003730037282873287671001020100002020000300373003711100221091010100001000010306402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqrdmulh v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224100000061295482510100100100001001000050042773131300183003730037282727287401010020010008200200163003730037111020110099100100100001001001117170160029647100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282727287411010020010008200200163003730037111020110099100100100001000001117170160029647100001003003830038300383003830038
10204300372250000000612954810410100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001002000007101161129634100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037224000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
10204300372250000900943295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129670100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010021116300008001160129634100001003027630278302753027730038
10204300372250006540440061295482510100100100001271000050042773131300183027630275282659287451010020010000200200003003730037111020110099100100100001003000007101161129634100001003003830038300383003830038
102043003722500001170061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010036402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830079300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqrdmulh v0.4s, v8.4s, v9.4s
  sqrdmulh v1.4s, v8.4s, v9.4s
  sqrdmulh v2.4s, v8.4s, v9.4s
  sqrdmulh v3.4s, v8.4s, v9.4s
  sqrdmulh v4.4s, v8.4s, v9.4s
  sqrdmulh v5.4s, v8.4s, v9.4s
  sqrdmulh v6.4s, v8.4s, v9.4s
  sqrdmulh v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000880622580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511021611200360800001002004020040200402004020040
8020420039150000001252580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
8020420039150000001812580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011614200360800001002004020040200402004020040
8020420039150000001482580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
8020420039150000005222580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011612200360800001002004020040200402004020040
802042003915000000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
8020420039150000001042580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000000622580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150172258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000050205444160422003680000102004020040200402004020040
8002420039150105258001010800001080000506400000520020200392003999963100198001020800002016000020039200391180021109101080000100000050205004170442003680000102004020040200402004020040
80024200391503262580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000000502052021602152003680000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001008400502000041604142003680000102004020040200402004020040
800242003915061258001010800001080000506400000020020200892003999963100198001020800002016000020039200391180021109101080000100000050205002160242003680000102004020040200402004020040
80024200391502302580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000000502004041602162003680000102004020040200402004020040
8002420039150187258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000100000050205002160252003680000102004020040200402004020040
80024200391501452580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001000000502000041602142003680000102004020040200402004020040
80024200391501662580010108000010800005064000015200202003920039999631001980010208000020160000200392003911800211091010800001000000502000031604142003680000102004020040200402004020040
8002420039150402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000000502005021604182003680000102004020040200402004020087