Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRSHL (vector, 2D)

Test 1: uops

Code:

  sqrshl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723000258254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030863038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100001073116112630100030383038303830383038
100430372200061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372200061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqrshl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
102043003722500009264061295482510100100100161001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000168295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037225000000084295482510100100100001001000050042773133001830037300372826573287451010020010000200200003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000000002662954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006441016101029630010000103003830038300383003830038
1002430037225000000000026629548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000064410168829630010000103003830038300383003830038
100243003722500000000035226629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000121206441016101029630010000103003830038300383003830323
100243037322800010067423528449792948516310073171006412108946642868121302703041730369283173528912110572411144242196630371303698110021109101010000100000021958008181775151429917210000103027330323303693036830371
100243030722800000088924616211029548251001010100001010000504277313030018300373003728287328767100102010497202000030037300371110021109101010000100031041649307951365152029848210000103017930368303693016930371
10024304172282003009812007922568429476182100881710064121121788428794613030630414304632832020289171120622113092222594304173041810110021109101010000102000002776006441116101329630610000103041830512305113046430500
10024304982290501118106877922651629458235100861710088231163960429224003041430548305582832332876710010201000020200003003730037111002110910101000010000000306441024101029915010000103003830038300383003830038
10024300852250100100001082592429494237100951510064101044750427731313001830037300372828732878210010201000020200003003730037111002110910101000010020044006448168529630010000103003830038300383003830038
100243003723201001000102026372954844100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006441016121129630010000103003830038300383003830038
1002430037225010010000021952954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006441116111229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  sqrshl v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313130018030037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100014471011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100017171011611296340100001003003830038300383003830038
1020430037224000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100012371011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100012371011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282870328745101002001000020020000300373003711102011009910010010000100014471011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100013871011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100013871011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100013271011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100014471011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640416342963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000222000030037300371110021109101010000100000640416432963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640316342963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640416432963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728292328767100102010000202000030037300371110021109101010000100600640316432963010000103003830038300383003830038
1002430037224000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640416442963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640316342963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130022300373003728287328767100102010000202000030037300371110021109101010000100000640216432963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000640316442963010000103003830038300383003830038
10024300372250100080929548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640416442963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqrshl v0.2d, v8.2d, v9.2d
  sqrshl v1.2d, v8.2d, v9.2d
  sqrshl v2.2d, v8.2d, v9.2d
  sqrshl v3.2d, v8.2d, v9.2d
  sqrshl v4.2d, v8.2d, v9.2d
  sqrshl v5.2d, v8.2d, v9.2d
  sqrshl v6.2d, v8.2d, v9.2d
  sqrshl v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000600051103161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000300051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400002002020039200709983399978010020080000200160000200392003911802011009910010080000100001817100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000012000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000010500051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000028300051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000001500051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100000000051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000022000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000012600051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000000402580010108000010800005064000011200202003920039999631001980010208000020160000200392003911800211091010800001000000050200416452003600080000102004020040200402004020040
80024200391500000300083525800101080000108000050640000112002020039200399996310019800102080000201600002003920039118002110910108000010000078050200216422003600080000102004020040200402004020040
80024200391500000000402580010108000010800005064000000200202008920039999631001980010208000020160000200392003911800211091010800001000010050200416432003600080000102004020040200402004020040
8002420039150000000011172580010108000010800005064000000200202003920090999631001980010208000020160000200392003911800211091010800001000003050200316732003600080000102004020040200402004020040
80024200391500000000632580010108000010800005064000011200202003920039999631001980010208000020160000200392003911800211091010800001000000050200416242003600080000102004020040200402004020040
800242003915000002100402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000006050200216472003600080000102004020040200402004020040
8002420039150110000040258001010800001080000506400000020020200392003999963100468001020800002016000020039200391180021109101080000100001516050200416422007400080000102004020040200402004020040
80024200391500000000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000006050200216242003600080000102004020040200402004020040
80024200391500000000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001002002370050940380632027330080000102024520293202852019620302
8002420293152015666044014025800101080000108000055643236012018220039200901002431007380537208030720161262201972009251800211091010800001022212350250910416442003600080000102009020295200402019220240