Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRSHL (vector, 8B)

Test 1: uops

Code:

  sqrshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000007573116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073124112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000008773116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000002773116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  sqrshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
102043003722500000120061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038
102043003722500000000103295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000073421622296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010220000279006402162229630010000103003830038300383008530086
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000010712954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430084225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300863003830038
100243003722500000028482954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000306402162229630010000103003830038300383017930038
10024300372250000306129548251001010100001010000504278670130306304123041328315392892711206221098120226003041230037111002110910101000010000000006402162229630010000103040730371303213041630464

Test 3: Latency 1->3

Code:

  sqrshl v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043075223010000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000030710011611296340100001003003830038300383003830038
102043003722500000061295484510223183101511801104383142976680300183003730132282683287451010020011161250203323003730133311020110099100100100001000010710011611296340100001003003830038300383003830038
1020430037225000000447295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730078111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722500000082295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037511020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722400000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722400000082295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612953925100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010106672160222963010000103003830038300383003830038
1002430037225000003462954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
1002430037239000004412954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
1002430037225000007262954825100101010000101000050427731303006530037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402160222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  sqrshl v0.8b, v8.8b, v9.8b
  sqrshl v1.8b, v8.8b, v9.8b
  sqrshl v2.8b, v8.8b, v9.8b
  sqrshl v3.8b, v8.8b, v9.8b
  sqrshl v4.8b, v8.8b, v9.8b
  sqrshl v5.8b, v8.8b, v9.8b
  sqrshl v6.8b, v8.8b, v9.8b
  sqrshl v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150412580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010005110002161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010005110001161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000010200202003920039997339997801002008031120016000020039200391180201100991001008000010005110001161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010065110521161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010005110521161120036800001002004020040200402004020040
80204200391506112580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010005110021161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010005110001161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000005200202003920039997339997801002008000020016041620039200391180201100991001008000010005110001161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000005200202003920039997339997801002008000020016000020039200391180201100991001008000010005110001161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010005110001161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110920023101080000100000050320001516000992003600080000102004020040200402004020040
80024200391500000000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010000005030000516000462003600080000102004020040200402004020040
800242003915000000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211090101080000100000050320003160005112003600080000102004020040200402004020040
80024200391500000000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109010108000010000005029000516000642003600080000102004020040200402004020040
80024200391500000000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010000005030000516000452003600080000102004020040200402004020040
80024200391500000000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010000005030000916000552003600080000102004020040200402004020040
8002420039150000000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000000502900041600011102003600080000102004020040200402004020040
8002420039150000000000776988001012803931280310566431921202162029820240100258100198052520804212016062020242202946180021109010108000010000005030000516000662003600080000102004020040200402004020040
800242003915000000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211090101080000100000050310001116000552003600080000102004020040200402004020040
800242003915000000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211090101080000100000050300009160004102003600080000102004020040200402004020040