Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRSHRN2 (2D)

Test 1: uops

Code:

  sqrshrn2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300126612548251000100010003983133018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372300147612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqrshrn2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722400000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722400000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100010710011611296340100001003003830038300383003830038
102043003722400000006129548251010010010000100100005004278675030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722400010016129548251010010410008100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003008530085301703003830086
10204300372250000010806129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722400000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000012006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372240006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225001986129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372251006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqrshrn2 v0.4s, v0.2d, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240001242954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117180160029629100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117180160029645100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373003728271628741101002001000820020016300373003711102011009910010010000100001117170170029646100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373008428271628740101002001000820020016300373003711102011009910010010000100001117170160029645100001003008630038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373003728284628741101002001000820020016300373003711102011009910010010000100001117170240029646100001003003830038300383003830038
1020430037225000612954725101001001000010210000500427716030018300373003728271628741101002021000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100001117180160029645100001003003830038300383003830038
1020430037224000612954725101001001000010010000500427716030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117170160029645100001003003830038300383003830038
1020530037225000612954725101001001000010010000500427716030018300373003728271628740101002001000820020016300373003711102011009910010010000100001117170160029646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000007932954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000001902954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000005922954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000007902954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000000026882954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243017922500000008892954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243003722500000008472954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010042748640216222962910000103003830038300383003830038
100243003722500000001662954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010003640216222962910000103003830038300383003830038
100243003722500000005792954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010200640216222962910000103003830038300383003830038
1002430037225000000052732954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383018130038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrn2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  sqrshrn2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  sqrshrn2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  sqrshrn2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  sqrshrn2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  sqrshrn2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  sqrshrn2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  sqrshrn2 v7.4s, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915011725801161008001610080028500640196120045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662017120066
160204200651512925801161008001610080028500640196120045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066
160204200651502925801161008001610080028500640196020045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066
160204200651502925801161008001610080028500640196120045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066
1602042006515011925801161008001610080028500640196020045020065200656508012820080028200160056200652006511160201100991001001600001000000911110119160200621600001002006620066201322006620066
1602042006515044825801161008001610080028500640196120045020065200656128012820080028200160056200652006511160201100991001001600001002200011110169160200621600001002006620066200662006620066
160204201571505025801161008001610080028500640196020045020065200656128012820080028200160056200652006521160201100991001001600001000000011110119160203851600001002006620066200662006620066
160204200651509425801161008001610080028500640196020045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066
160204200651509625801161008001610080028500640196020045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066
160204200651502925801161008001610080028500640196020045020065200656128012820080028200160056200652006511160201100991001001600001000000011110119160200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200741500196104800101080000108000050640000110200312005020046322800102080000201600002004620046111600211091010160000100010028311820211542005115160000102004720047200472004720047
1600242004615004525800101080000108000050640000110200272004620050322800102080000201600002004620046111600211091010160000100010033311420412772005115160000102004720047200472004720047
1600242004615004525800101080000108000050640000110200272004620046322800102080000201600002005020050111600211091010160000101010028322820421552005115160000102016820047200472004720047
16002420046150010825800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000101010028311520211772006415160000102004720047200472004720047
1600242004615004525800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000100010028321520411782005130160000102005120047200472004720047
1600242004615004525800101080000108000050640000010200312005020130322800102080000201600002005020050111600211091010160000100010028311520211772005130160000102005120051200512005120051
16002420050150037425800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000100010028311520211552006430160000102005120051200472004720047
16002420046150046525800101080000108000050640000010200272004620046322800102080000201600002004620046111600211091010160000100010027312820412552006330160000102004720047200472004720047
160024200461501245658001010800001080000506400001102009320046200461164800102080000201600002004620046111600211091010160000100010053311753211452011715160000102004720047200472004720047
160024200461501243825800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000101010028311520211982006415160000102005120051200512005120047

Test 5: throughput

Count: 16

Code:

  sqrshrn2 v0.4s, v16.2d, #3
  sqrshrn2 v1.4s, v16.2d, #3
  sqrshrn2 v2.4s, v16.2d, #3
  sqrshrn2 v3.4s, v16.2d, #3
  sqrshrn2 v4.4s, v16.2d, #3
  sqrshrn2 v5.4s, v16.2d, #3
  sqrshrn2 v6.4s, v16.2d, #3
  sqrshrn2 v7.4s, v16.2d, #3
  sqrshrn2 v8.4s, v16.2d, #3
  sqrshrn2 v9.4s, v16.2d, #3
  sqrshrn2 v10.4s, v16.2d, #3
  sqrshrn2 v11.4s, v16.2d, #3
  sqrshrn2 v12.4s, v16.2d, #3
  sqrshrn2 v13.4s, v16.2d, #3
  sqrshrn2 v14.4s, v16.2d, #3
  sqrshrn2 v15.4s, v16.2d, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044005830000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001004001111011811611400361600001004004040040400404004040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400894003911160201100991001001600001000001111011811611400361600001004004040040400404009040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
16020440039300000300251601081001600081001600205001281796401504021940216200051520042160323202160341200320678401934019441160201100991001001600001000214651111017125021401161600001004016240174401674016540211
160204400393000012536025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
1602044003930000030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040
1602044003929900030025160108100160008100160020500128013240020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011811611400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400492990046251600101016000010160000501280000104002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231131621105540036306160000104004040040400404004040040
1600244003929900711251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002462251642114540036156160000104004040040400404004040040
160024400393000046251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231141621113340036156160000104004040040400404004040040
160024400392990046251600101016000010160000501280000014002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231131621114340036156160000104004040040400404004040040
160024400393000052251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002232241621104440036156160000104004040040400404004040040
160024400393000046251600101016000010160000501280000014002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231141641164540036156160000104004040040400404004040040
160024400392990046251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231141621104340036306160000104004040040400404004040040
160024400393000046251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231161621124340036156160000104004040040400404004040040
160024400393000046251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231141621104540036156160000104004040040400404004040040
160024400393000046251600101016000010160000501280000114002040039400391998903200121600102016000020320000400394003911160021109101016000010001002231141621113340036156160000104004040040400404004040040