Firestorm: SQRSHRN2 (2D) measurements

Code:

  sqrshrn2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	126	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	147	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrshrn2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4278675	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	1	0	0	1	61	29548	25	10100	104	10008	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30085	30085	30170	30038	30086
10204	30037	225	0	0	0	0	0	108	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	12	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	198	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrshrn2 v0.4s, v0.2d, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	0	124	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	17	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30084	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30086	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28284	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	24	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	102	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	202	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10205	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	793	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	190	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	592	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	790	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	2688	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30179	225	0	0	0	0	0	0	0	889	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	847	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	4	2748	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	166	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	579	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	5273	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30181	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrn2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  sqrshrn2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  sqrshrn2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  sqrshrn2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  sqrshrn2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  sqrshrn2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  sqrshrn2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  sqrshrn2 v7.4s, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	117	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20171	20066
160204	20065	151	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	119	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	50	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	9	1	1	1	10119	16	0	20062	160000	100	20066	20066	20132	20066	20066
160204	20065	150	448	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	2	0	0	0	1	1	1	10169	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20157	150	50	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20385	160000	100	20066	20066	20066	20066	20066
160204	20065	150	94	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	96	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20074	150	0	196	104	80010	10	80000	10	80000	50	640000	1	1	0	20031	20050	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	8	20	2	1	1	5	4	20051	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20050	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10033	3	1	1	4	20	4	1	2	7	7	20051	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	1	0	10028	3	2	2	8	20	4	2	1	5	5	20051	15	160000	10	20168	20047	20047	20047	20047
160024	20046	150	0	108	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	1	0	10028	3	1	1	5	20	2	1	1	7	7	20064	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	2	1	5	20	4	1	1	7	8	20051	30	160000	10	20051	20047	20047	20047	20047
160024	20046	150	0	45	25	80010	10	80000	10	80000	50	640000	0	1	0	20031	20050	20130	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	5	20	2	1	1	7	7	20051	30	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	374	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	5	20	2	1	1	5	5	20064	30	160000	10	20051	20051	20047	20047	20047
160024	20046	150	0	465	25	80010	10	80000	10	80000	50	640000	0	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10027	3	1	2	8	20	4	1	2	5	5	20063	30	160000	10	20047	20047	20047	20047	20047
160024	20046	150	12	45	65	80010	10	80000	10	80000	50	640000	1	1	0	20093	20046	20046	11	64	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10053	3	1	1	7	53	2	1	1	4	5	20117	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	12	438	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	1	0	10028	3	1	1	5	20	2	1	1	9	8	20064	15	160000	10	20051	20051	20051	20051	20047

Test 5: throughput

Count: 16

Code:

  sqrshrn2 v0.4s, v16.2d, #3
  sqrshrn2 v1.4s, v16.2d, #3
  sqrshrn2 v2.4s, v16.2d, #3
  sqrshrn2 v3.4s, v16.2d, #3
  sqrshrn2 v4.4s, v16.2d, #3
  sqrshrn2 v5.4s, v16.2d, #3
  sqrshrn2 v6.4s, v16.2d, #3
  sqrshrn2 v7.4s, v16.2d, #3
  sqrshrn2 v8.4s, v16.2d, #3
  sqrshrn2 v9.4s, v16.2d, #3
  sqrshrn2 v10.4s, v16.2d, #3
  sqrshrn2 v11.4s, v16.2d, #3
  sqrshrn2 v12.4s, v16.2d, #3
  sqrshrn2 v13.4s, v16.2d, #3
  sqrshrn2 v14.4s, v16.2d, #3
  sqrshrn2 v15.4s, v16.2d, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	4	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40089	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40090	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1281796	40150	40219	40216	20005	15	20042	160323	202	160341	200	320678	40193	40194	4	1	160201	100	99	100	100	160000	100	0	2	1465	1	1	1	10171	2	50	2	1	40116	160000	100	40162	40174	40167	40165	40211
160204	40039	300	0	0	12	536	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	30	0	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	299	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	3	16	2	1	10	5	5	40036	30	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	711	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10024	6	2	2	5	16	4	2	11	4	5	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	2	1	11	3	3	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	3	16	2	1	11	4	3	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	2	2	4	16	2	1	10	4	4	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	4	1	16	4	5	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	2	1	10	4	3	40036	30	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	6	16	2	1	12	4	3	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	2	1	10	4	5	40036	15	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19989	0	3	20012	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	4	16	2	1	11	3	3	40036	15	6	160000	10	40040	40040	40040	40040	40040

SQRSHRN2 (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations