Firestorm: SQRSHRN2 (8H) measurements

Code:

  sqrshrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	105	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	147	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrshrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	3	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	1	0	0	0	1463	29548	25	10100	100	10000	100	10000	500	4278670	0	30018	30037	30132	28269	8	28745	10100	200	10331	200	20668	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	82	29548	25	10100	100	10000	100	10000	500	4277313	0	30342	30465	30452	28293	42	28907	11491	228	11488	228	22982	30464	30469	10	1	10201	100	99	100	100	10000	100	0	2	24973	912	1	109	1	2	29941	29	10000	100	30465	30465	30465	30511	30468
10204	30467	228	0	10	10	1188	792	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28276	48	28901	11488	200	10662	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	12	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30078	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30084	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30084	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	75	0	631	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrshrn2 v0.16b, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	718	0	24	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	97	29538	45	10110	100	10008	102	10150	511	4279864	0	30054	30133	30134	28256	10	28770	10406	208	10164	202	20332	30085	30086	2	1	10201	100	99	100	100	10000	100	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4281216	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrn2 v0.16b, v8.8h, #3
  movi v1.16b, 0
  sqrshrn2 v1.16b, v8.8h, #3
  movi v2.16b, 0
  sqrshrn2 v2.16b, v8.8h, #3
  movi v3.16b, 0
  sqrshrn2 v3.16b, v8.8h, #3
  movi v4.16b, 0
  sqrshrn2 v4.16b, v8.8h, #3
  movi v5.16b, 0
  sqrshrn2 v5.16b, v8.8h, #3
  movi v6.16b, 0
  sqrshrn2 v6.16b, v8.8h, #3
  movi v7.16b, 0
  sqrshrn2 v7.16b, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	151	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10127	5	1	8	16	0	7	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	3	0	1	1	1	10127	0	0	8	16	0	8	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	9	0	0	29	25	80116	100	80016	100	80028	500	640196	0	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	12	0	1	1	1	10127	0	0	8	16	0	8	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	24	0	1	1	1	10127	0	0	7	16	0	8	3	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	28	80116	100	80016	100	80028	500	640196	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10122	0	0	3	16	0	3	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	3	0	1	1	1	10127	0	0	8	16	0	8	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	4	0	0	0	1	1	1	10127	5	0	8	16	0	8	9	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	3	0	1	1	1	10126	5	0	8	16	0	8	3	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	0	0	1	1	1	10126	0	1	3	16	3	8	8	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	5	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	3	0	1	1	1	10127	5	0	8	16	0	8	8	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20069	150	2	0	1	0	0	0	57	79	80010	10	80000	10	80000	50	640000	1	1	5	20034	20051	20051	3	22	80010	20	80000	20	160000	20051	20053	1	1	160021	10	9	10	10	160000	10	0	0	15	0	10042	13	1	1	23	27	1	1	1	20	18	20048	20	1	160000	10	20054	20052	20052	20052	20052
160024	20053	150	1	0	1	0	0	0	247	84	80010	10	80000	10	80000	50	640000	1	1	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10038	13	4	1	20	25	1	1	1	19	16	20048	21	1	160000	10	20054	20054	20052	20052	20061
160024	20051	151	1	0	1	0	0	0	51	75	80010	10	80000	10	80000	50	640000	1	1	10	20032	20051	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10041	13	3	1	19	25	2	1	2	17	17	20048	20	1	160000	10	20054	20052	20054	20052	20052
160024	20053	150	2	0	1	0	0	0	51	95	80010	10	80000	10	80000	50	640000	1	1	10	20034	20053	20053	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10042	13	3	1	16	25	2	1	1	18	22	20050	20	1	160000	10	20052	20052	20054	20054	20052
160024	20053	150	2	0	3	0	0	0	51	74	80010	10	80000	10	80000	50	640000	1	1	10	20034	20051	20053	3	22	80010	20	80000	20	160000	20053	20051	1	1	160021	10	9	10	10	160000	10	0	0	135	0	10042	13	3	1	18	25	2	1	1	21	18	20048	20	1	160000	10	20052	20054	20054	20052	20052
160024	20051	150	4	0	2	0	0	0	57	74	80010	10	80000	10	80000	50	640000	1	1	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20053	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10039	13	3	1	22	27	2	1	1	17	21	20048	21	1	160000	10	20054	20052	20054	20054	20052
160024	20053	151	2	0	2	1	0	0	74	70	80010	10	80000	10	80000	50	640000	1	1	10	20032	20053	20051	3	22	80010	20	80000	20	160000	20051	20053	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10040	13	3	1	20	27	1	1	1	19	18	20050	20	1	160000	10	20052	20052	20052	20052	20054
160024	20051	150	2	0	2	0	0	0	45	74	80010	10	80000	10	80000	50	640000	1	1	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	35	0	0	10039	16	3	1	18	25	1	1	1	19	20	20050	21	1	160000	10	20052	20052	20061	20061	20068
160024	20053	150	1	0	0	0	0	0	51	74	80010	10	80000	10	80000	50	640000	1	1	10	20032	20051	20051	3	22	80010	20	80000	20	160000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10045	13	3	1	24	25	2	1	1	19	21	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	151	1	0	1	0	0	0	57	74	80010	10	80000	10	80000	50	640000	1	1	10	20032	20053	20053	3	22	80010	20	80000	20	160270	20053	20051	1	1	160021	10	9	10	10	160000	10	0	1	3	0	10038	13	5	1	18	25	2	1	1	21	18	20048	20	1	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  sqrshrn2 v0.16b, v16.8h, #3
  sqrshrn2 v1.16b, v16.8h, #3
  sqrshrn2 v2.16b, v16.8h, #3
  sqrshrn2 v3.16b, v16.8h, #3
  sqrshrn2 v4.16b, v16.8h, #3
  sqrshrn2 v5.16b, v16.8h, #3
  sqrshrn2 v6.16b, v16.8h, #3
  sqrshrn2 v7.16b, v16.8h, #3
  sqrshrn2 v8.16b, v16.8h, #3
  sqrshrn2 v9.16b, v16.8h, #3
  sqrshrn2 v10.16b, v16.8h, #3
  sqrshrn2 v11.16b, v16.8h, #3
  sqrshrn2 v12.16b, v16.8h, #3
  sqrshrn2 v13.16b, v16.8h, #3
  sqrshrn2 v14.16b, v16.8h, #3
  sqrshrn2 v15.16b, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	0	0	0	0	9	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	5	0	3	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	0	0	0	0	0	35	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	505	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	0	0	51	46	160116	100	160016	100	160028	500	1283404	1	40029	40100	40264	19986	10	19986	160128	200	160000	200	320000	40099	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	0	6	0	1	1	1	10120	4	24	3	4	40166	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	3	0	206	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	0	1	1	1	10120	4	24	4	4	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	1	0	0	76	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10120	3	33	4	4	40045	160000	100	40049	40049	40049	40049	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	299	2	0	1	0	0	0	0	0	124	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10025	8	1	1	2	48	16	1	1	1	43	41	40036	16	5	160000	10	40040	40076	40040	40040	40040
160024	40039	299	2	0	1	0	0	0	0	0	95	25	160010	10	160000	10	160000	50	1280000	0	1	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	3	0	0	10026	3	5	2	2	47	16	3	2	1	41	35	40036	31	10	160000	10	40040	40084	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	0	1	683	63	160303	10	160292	10	160307	50	1281600	1	0	5	40115	40039	40039	19996	3	20019	160319	20	160104	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	2	1	0	1450	10104	8	4	1	2	46	81	1	1	1	45	37	40124	16	5	160000	10	40202	40197	40191	40148	40206
160024	40089	301	2	0	1	0	0	0	0	0	118	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	2	0	0	10025	8	4	1	2	47	16	1	1	1	46	31	40036	16	5	160000	10	40040	40094	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	0	1	118	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10025	8	4	1	2	45	16	1	1	1	45	45	40036	16	5	160000	10	40040	40103	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	0	1	124	25	160010	10	160000	10	160000	50	1280000	1	0	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10025	8	4	1	2	32	16	1	1	1	37	46	40036	16	5	160000	10	40040	40089	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	88	1	124	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10024	8	4	1	2	45	16	1	1	1	46	31	40036	16	5	160000	10	40040	40089	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	0	0	124	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10025	8	4	1	2	31	16	3	1	1	43	46	40036	16	5	160000	10	40040	40089	40040	40040	40194
160024	40039	300	2	0	1	0	0	0	0	0	118	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160114	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	3	0	0	10024	8	4	1	2	44	16	1	1	1	43	44	40036	16	5	160000	10	40040	40094	40040	40040	40040
160024	40039	300	2	0	1	0	0	0	0	1	124	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10024	3	1	1	2	36	16	1	1	1	46	36	40036	16	5	160000	10	40040	40089	40040	40040	40040

SQRSHRN2 (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations