Firestorm: SQRSHRN (H) measurements

Code:

  sqrshrn b0, h0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	1	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	198	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	3	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  sqrshrn b0, h0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	710	1	16	1	1	29666	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	202	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	631	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	726	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	4	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	0	156	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30510	228	0	0	0	9	11	1320	880	6589	29448	213	10096	12	10088	16	11650	55	4289328	0	30342	30510	30514	28322	43	28944	11511	22	11805	26	10332	30513	30511	11	1	10021	10	9	10	10	10000	10	4	0	0	8	0	27760	0	855	5	105	2	2	30049	3	10000	10	30559	30510	30508	30499	30548
10024	30508	229	0	1	0	8	10	1320	528	6507	29457	205	10078	15	10088	13	11500	82	4290680	0	30342	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	23	0	9	4	808	3	80	6	1	29955	4	10000	10	30416	30417	30180	30510	30463
10024	30463	229	0	0	0	8	9	1056	792	5226	29547	25	10010	10	10000	10	10000	65	4287976	0	30342	30037	30037	28317	41	28919	11368	26	11313	22	11482	30462	30415	10	1	10021	10	9	10	10	10000	10	2	2	2	24	0	24918	0	810	5	88	4	3	29934	4	10000	10	30465	30457	30500	30465	30469
10024	30460	227	1	1	0	10	9	1188	792	6044	29475	191	10087	14	10072	20	11200	76	4287976	0	30270	30368	30368	28317	34	28880	11062	24	11157	22	10492	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	21	0	3	0	640	2	72	2	2	29629	3	10000	10	30038	30177	30372	30367	30085
10024	30179	227	1	0	0	3	3	540	352	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	7	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	36	0	16788	2	812	3	65	3	2	29917	3	10000	10	30179	30464	30273	30418	30274
10024	30402	227	1	1	0	4	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	34	0	0	0	661	1	24	3	2	29770	3	10000	10	30227	30227	30179	30178	30371
10024	30370	227	1	1	1	3	3	408	280	1343	29511	44	10028	13	10016	12	10300	71	4279864	0	30054	30085	30130	28293	7	28805	10609	20	10336	20	10249	30133	30133	3	1	10021	10	9	10	10	10000	10	4	2	0	1	4	2813	0	640	2	24	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	46	0	3	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	34	0	0	0	640	2	16	2	2	29667	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	1	1	6	88	61	29547	62	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	2	27	2	5570	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  sqrshrn b0, h8, #3
  sqrshrn b1, h8, #3
  sqrshrn b2, h8, #3
  sqrshrn b3, h8, #3
  sqrshrn b4, h8, #3
  sqrshrn b5, h8, #3
  sqrshrn b6, h8, #3
  sqrshrn b7, h8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	155	0	0	0	0	0	0	18	0	0	283	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	108	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20051	150	0	1	1	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5024	0	21	16	7	11	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	123	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	2	6	0	5024	0	9	16	11	7	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5024	6	8	16	6	10	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	9	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5024	0	10	16	8	5	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	2	0	0	0	5024	0	7	16	7	8	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5024	0	8	16	7	10	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	63	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5026	0	9	16	9	5	5	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	1	0	0	0	5028	0	5	16	9	4	5	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	1	0	0	0	5024	0	6	16	7	7	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5026	0	6	16	6	11	4	20036	80000	10	20040	20040	20040	20040	20040

SQRSHRN (H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations