Firestorm: SQRSHRN (S) measurements

Code:

  sqrshrn h0, s0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	147	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	1	92	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	82	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	126	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	3	73	2	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	100	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	84	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	73	3	16	3	3	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  sqrshrn h0, s0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	232	0	0	0	0	0	0	0	0	234	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10166	30037	30037	1	1	10201	100	99	100	100	10000	100	0	4	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	1	0	0	0	229	29547	20	44	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10330	200	10000	30037	30037	4	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	18	28761	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30133	30038
10204	30037	232	0	0	0	0	0	0	0	0	61	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30086
10204	30037	233	0	0	0	0	0	0	0	0	103	29547	0	25	10100	100	10000	100	10000	602	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	726	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	0	0	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30135	30038
10204	30037	233	0	0	0	0	0	0	0	0	84	29547	0	62	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29633	12	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	1	84	29547	0	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30083	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	2	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bc	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	1	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	40	0	6	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	242	0	0	0	0	0	0	0	0	97	29547	25	10010	10	10000	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	0	2210	0	0	640	2	16	2	2	29629	0	10000	10	30038	30086	30085	30038	30038
10024	30037	232	0	0	0	1	0	0	0	0	61	29547	25	10010	10	10008	11	10150	82	0	4279864	1	30054	30084	30084	28290	8	28786	10163	20	10162	22	10168	30084	30085	2	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	2	2738	0	2	661	2	24	3	3	29667	2	10000	10	30133	30131	30133	30133	30086
10024	30178	233	0	0	0	0	0	0	0	0	1332	29529	43	10030	15	10008	10	10150	55	0	4278512	1	30018	30131	30037	28286	3	28779	10010	20	10000	22	10000	30180	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	2613	0	4	661	3	32	2	2	29629	0	10000	10	30038	30085	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	1	103	29547	43	10020	12	10000	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	0	9	0	0	640	2	16	2	2	29667	0	10000	10	30133	30134	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	726	29547	25	10010	10	10000	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	2	9	0	0	640	3	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	247	0	0	0	0	0	0	0	0	1407	29547	25	10010	10	10008	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	207	0	0	61	29547	25	10010	10	10000	10	10150	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2	0	9	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30085	30038	30038
10024	30037	234	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10450	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	0	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	3	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  sqrshrn h0, s8, #3
  sqrshrn h1, s8, #3
  sqrshrn h2, s8, #3
  sqrshrn h3, s8, #3
  sqrshrn h4, s8, #3
  sqrshrn h5, s8, #3
  sqrshrn h6, s8, #3
  sqrshrn h7, s8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20060	155	1	0	1	0	0	0	0	0	86	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	2	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	161	1	0	1	0	0	1	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	2	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	156	1	0	1	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	11	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20176	20040	20091	20040	20040
80204	20039	155	1	0	1	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80137	20111	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	1	0	1	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	1	0	1	0	0	0	0	0	695	25	80108	100	80008	100	80020	511	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	1	0	1	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	156	1	0	1	0	0	0	0	0	30	25	80502	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	1	0	1	0	1	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20039	1	1	80201	100	99	100	100	80000	100	0	2	0	0	1	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	155	1	0	1	0	0	0	9	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	80032	20039	20104	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	0	0	1	1	1	5118	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20094

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	161	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	87	0	5020	4	16	4	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	160	0	0	0	0	0	9	0	0	167	25	80010	10	80000	10	80000	50	643324	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	2	0	0	0	0	0	0	5020	4	16	4	2	20086	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	75	0	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	0	20039	20039	9996	8	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	81	0	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	87	0	5020	4	39	2	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	156	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	78	0	5020	5	16	4	2	20036	80000	10	20040	20040	20040	20040	20090
80024	20039	156	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	84	0	5020	2	16	2	4	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	1	40	25	80010	10	80000	10	80000	50	640000	0	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	4	16	4	2	20036	80000	10	20040	20144	20040	20040	20040
80024	20039	155	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	935	0	5020	4	16	4	2	20036	80000	10	20040	20040	20040	20040	20040

SQRSHRN (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations