Firestorm: SQRSHRUN2 (2D) measurements

Code:

  sqrshrun2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	147	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	4	0	73	3	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3073	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	758	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrshrun2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	392	29548	25	10100	100	10008	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	39	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	204	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10267	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	24	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	2	0	0	0	208	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	226	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30086	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrshrun2 v0.4s, v0.2d, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	27	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	9	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	6	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	51	726	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	42	61	29547	25	10010	10	10000	10	10150	50	4277160	1	30018	30084	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	661	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	33	61	29547	25	10018	12	10000	10	10300	61	4277160	1	30018	30037	30037	28291	7	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	36	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	6	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	12	61	29538	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30085	30084	1	1	10021	10	9	10	10	10000	10	1	4	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	537	103	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10025	30037	225	0	0	18	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	33	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrun2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  sqrshrun2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  sqrshrun2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  sqrshrun2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  sqrshrun2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  sqrshrun2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  sqrshrun2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  sqrshrun2 v7.4s, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	0	0	0	9	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20229	2	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80324	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	13	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	36	0	694	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20074	151	1	0	0	0	42	0	0	51	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20060	20051	0	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	8	4	2	37	25	2	1	1	13	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	6	0	0	950	186	80432	10	80417	10	80527	50	644216	1	0	5	20356	20458	20453	0	33	128	80537	20	80526	20	161048	20462	20460	6	1	160021	10	9	10	10	160000	10	0	4	1	0	2193	10138	8	5	2	15	202	4	2	1	19	24	20428	20	2	160000	10	20508	20451	20458	20449	20456
160024	20451	150	0	0	0	0	33	0	0	45	27	80115	10	80000	10	80000	50	640000	0	0	5	20041	20060	20060	0	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	1	0	3	10063	8	5	1	13	25	2	1	1	22	15	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	12	0	1	129	27	80010	10	80000	10	80000	50	645888	1	1	5	20550	20608	20691	0	70	128	80432	20	80628	24	160630	20855	20508	11	1	160021	10	9	10	10	160000	10	4	0	0	4	4225	10303	3	1	1	12	247	2	1	1	22	16	20814	15	0	160000	10	20908	20849	20907	20938	20047
160024	21014	159	0	1	11	9	1584	440	0	45	25	80010	10	80000	10	80000	50	640840	1	1	0	20027	20046	20046	0	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	12	10036	3	1	1	13	20	2	1	1	13	13	20043	15	0	160000	10	20047	20047	20047	20050	20047
160024	20046	151	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20029	20046	20046	0	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10039	6	2	2	13	24	4	2	2	10	12	20047	30	0	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	51	25	80010	10	80000	10	80000	50	640000	0	1	0	20027	20046	20046	0	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	10037	6	2	2	15	24	4	2	2	20	12	20047	30	0	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	9	0	0	51	25	80010	10	80000	10	80000	50	640000	0	1	5	20031	20046	20050	0	3	22	80010	20	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10037	8	2	1	14	20	2	1	1	13	13	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	0	1	5	20027	20046	20046	0	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	8	2	1	13	20	2	1	1	13	16	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	0	3	22	80010	20	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	11	3	2	17	20	4	1	2	13	13	20043	15	0	160000	10	20047	20047	20051	20047	20047

Test 5: throughput

Count: 16

Code:

  sqrshrun2 v0.4s, v16.2d, #3
  sqrshrun2 v1.4s, v16.2d, #3
  sqrshrun2 v2.4s, v16.2d, #3
  sqrshrun2 v3.4s, v16.2d, #3
  sqrshrun2 v4.4s, v16.2d, #3
  sqrshrun2 v5.4s, v16.2d, #3
  sqrshrun2 v6.4s, v16.2d, #3
  sqrshrun2 v7.4s, v16.2d, #3
  sqrshrun2 v8.4s, v16.2d, #3
  sqrshrun2 v9.4s, v16.2d, #3
  sqrshrun2 v10.4s, v16.2d, #3
  sqrshrun2 v11.4s, v16.2d, #3
  sqrshrun2 v12.4s, v16.2d, #3
  sqrshrun2 v13.4s, v16.2d, #3
  sqrshrun2 v14.4s, v16.2d, #3
  sqrshrun2 v15.4s, v16.2d, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	0	0	0	0	0	0	0	0	0	912	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10129	1	23	1	1	40046	0	160000	100	40050	40050	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	1	40029	40048	40048	19976	0	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	2	23	1	1	40046	0	160000	100	40050	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	0	40029	40048	40048	19976	0	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	2	23	2	2	40045	0	160000	100	40050	40050	40049	40049	40049
160204	40049	300	0	0	0	0	0	0	0	0	0	0	64	27	160116	100	160016	100	160028	500	1280196	0	40029	40049	40048	19976	0	9	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	2	1	40045	0	160000	100	40050	40050	40049	40049	40050
160204	40049	300	0	0	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	1	40029	40049	40048	19976	0	10	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	2	2	40045	0	160000	100	40049	40050	40049	40049	40050
160204	40048	300	0	0	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	1	40029	40048	40048	19976	0	10	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40046	0	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	1	40029	40048	40049	19976	0	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10129	1	23	1	1	40046	0	160000	100	40049	40050	40050	40050	40050
160204	40048	300	0	0	0	0	0	0	0	0	0	0	64	27	160116	100	160016	100	160028	500	1280196	1	40029	40048	40048	19976	0	10	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40046	0	160000	100	40050	40050	40049	40049	40049
160204	40048	299	0	0	0	0	0	0	0	0	0	0	64	27	160116	100	160016	100	160028	500	1280196	0	40029	40048	40048	19976	0	10	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40045	0	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	0	6	0	0	464	65	160314	100	160213	102	160238	500	1281832	1	40029	40048	40048	19987	0	18	20039	160339	200	160243	202	320496	40160	40208	4	1	160201	100	99	100	100	160000	100	2	4	2	0	2	1445	2	2	2	10163	1	75	1	1	40112	0	160000	100	40172	40174	40152	40212	40212

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	3	1	5	16	2	1	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	1	0	337	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	4	16	2	2	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	0	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	2	16	2	2	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	2	16	2	1	1	4	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160112	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	8	4	1	2	16	2	1	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	7	3	20019	160010	20	160000	20	320000	40089	40039	2	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	4	16	2	1	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	2	16	2	1	1	6	4	40036	0	20	6	160000	10	40091	40040	40040	40040	40040
160024	40039	299	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	4	1	4	16	2	1	1	4	2	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	9	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	11	4	1	2	16	2	1	1	2	4	40036	0	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	15	0	10022	8	4	1	4	16	2	1	1	4	4	40036	0	40	6	160000	10	40040	40040	40040	40040	40040

SQRSHRUN2 (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations