Firestorm: SQRSHRUN2 (4S) measurements

Code:

  sqrshrun2 v0.8h, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	6	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	30	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	57	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	66	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	54	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	21	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqrshrun2 v0.8h, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	536	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	6	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	726	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	1	1	29634	8	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4281384	30018	30037	30037	28265	0	32	28889	11188	228	10497	228	22664	30444	30421	9	1	10201	100	99	100	100	10000	100	2	1	22148	2	890	3	101	2	1	29927	28	10000	100	30420	30468	30419	30423	30417
10204	30420	228	8	8	1068	704	5235	29485	162	10207	143	10072	142	11192	715	4289526	30342	30273	30417	28295	0	39	28817	11336	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	6	2	730	1	50	2	1	29814	30	10000	100	30323	30324	30230	30323	30276
10204	30277	227	6	5	534	264	2108	29548	44	10100	100	10000	122	10000	500	4277313	30018	30037	30037	28271	0	15	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	15	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	7	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	6	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	680	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	6	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	642	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	30	0	0	61	29548	25	10012	10	10000	10	10149	50	4277313	0	30018	30037	30037	28287	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2738	0	0	640	4	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	12	0	0	103	29548	25	10010	10	10000	10	10000	60	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	642	3	16	2	4	29630	2	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	103	29548	25	10010	10	10000	10	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30180	28287	3	28767	10159	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	65	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	9	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	12	10000	12	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	30	0	0	640	2	16	2	2	29630	2	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	60	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqrshrun2 v0.8h, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	3	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	3	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29547	25	10100	100	10000	106	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	6	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	3	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	3	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	48	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30085	30038
10204	30037	225	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	722	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	12	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	6	640	4	16	4	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	22	3	640	4	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	3	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	12	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	6	640	3	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	640	3	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	4	16	4	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	4	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	3	640	4	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	4	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10172	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	25	3	640	3	16	3	4	29629	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrun2 v0.8h, v8.4s, #3
  movi v1.16b, 0
  sqrshrun2 v1.8h, v8.4s, #3
  movi v2.16b, 0
  sqrshrun2 v2.8h, v8.4s, #3
  movi v3.16b, 0
  sqrshrun2 v3.8h, v8.4s, #3
  movi v4.16b, 0
  sqrshrun2 v4.8h, v8.4s, #3
  movi v5.16b, 0
  sqrshrun2 v5.8h, v8.4s, #3
  movi v6.16b, 0
  sqrshrun2 v6.8h, v8.4s, #3
  movi v7.16b, 0
  sqrshrun2 v7.8h, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10122	0	3	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	3	1	1	1	10122	0	4	16	5	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10122	0	5	16	4	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10122	0	5	16	5	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	15	6	1	1	1	10123	0	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10122	0	4	16	4	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10123	0	5	16	5	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10123	0	4	16	4	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10122	0	4	16	4	5	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	3	1	1	1	10122	0	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	0	1	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20062	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	21	10032	6	2	2	5	34	2	1	1	6	5	20048	40	1	160000	10	20052	20052	20052	20052	20052
160024	20062	150	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10029	3	1	1	6	25	2	1	1	6	7	20048	20	1	160000	10	20052	20052	20061	20052	20052
160024	20051	150	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	3	10028	6	1	1	9	25	2	1	1	6	6	20048	20	2	160000	10	20052	20052	20052	20052	20052
160024	20062	150	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	2	0	0	1	0	15	10029	3	1	1	5	25	3	1	1	8	5	20048	20	1	160000	10	20052	20131	20133	20052	20061
160024	20051	150	1	0	15	0	45	29	80114	12	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	6	10029	3	1	1	6	25	2	1	1	6	5	20048	20	1	160000	10	20052	20052	20052	20063	20052
160024	20051	150	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	6	10028	3	1	1	7	25	2	1	1	6	7	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20060	150	0	0	12	0	45	33	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10030	3	1	1	6	25	2	1	1	6	8	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	45	29	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1	0	3	10029	3	1	1	6	25	2	1	1	5	7	20048	20	1	160000	10	20052	20052	20052	20052	20061
160024	20060	150	0	0	21	0	45	244	80638	10	80630	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	18	0	36	10031	3	1	1	8	25	2	1	1	6	5	20048	20	2	160000	10	20052	20052	20052	20052	20052
160024	20060	163	0	0	0	0	185	33	80010	10	80000	10	80000	50	640000	1	1	20032	0	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10030	3	1	1	7	25	2	1	1	5	4	20048	41	1	160000	10	20052	20052	20052	20052	20063

Test 5: throughput

Count: 16

Code:

  sqrshrun2 v0.8h, v16.4s, #3
  sqrshrun2 v1.8h, v16.4s, #3
  sqrshrun2 v2.8h, v16.4s, #3
  sqrshrun2 v3.8h, v16.4s, #3
  sqrshrun2 v4.8h, v16.4s, #3
  sqrshrun2 v5.8h, v16.4s, #3
  sqrshrun2 v6.8h, v16.4s, #3
  sqrshrun2 v7.8h, v16.4s, #3
  sqrshrun2 v8.8h, v16.4s, #3
  sqrshrun2 v9.8h, v16.4s, #3
  sqrshrun2 v10.8h, v16.4s, #3
  sqrshrun2 v11.8h, v16.4s, #3
  sqrshrun2 v12.8h, v16.4s, #3
  sqrshrun2 v13.8h, v16.4s, #3
  sqrshrun2 v14.8h, v16.4s, #3
  sqrshrun2 v15.8h, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1281012	1	40020	40039	40039	19977	6	20017	160120	200	160032	200	320064	40039	40346	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40346	40101	40091	40402
160204	40559	304	1	5	9	1323	880	1834	212	160987	102	160693	100	161048	511	1287480	1	40434	40299	40496	20069	38	20207	161147	200	160550	202	322128	40580	40611	11	1	160201	100	99	100	100	160000	100	2	2	1	2	4721	2	2	1	10291	0	3	170	4	5	40564	1	160000	100	40726	40724	40721	40724	40679
160204	40407	305	1	13	12	1587	1056	1368	251	161369	100	161264	102	161239	522	1290504	1	40550	40667	40358	20074	35	20313	161330	200	160000	200	320000	40098	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10120	0	2	24	2	2	40045	0	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	1	3	0	76	27	160100	100	160000	100	160000	500	1280000	0	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10120	0	2	24	2	2	40045	0	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	27	0	160	27	160100	100	160000	100	160000	500	1280000	1	40029	40048	40048	19971	6	19994	160100	200	160000	200	320000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	1	1	1	10120	36	3	23	1	1	40045	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	1038	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	505	25	160108	100	160008	100	160020	500	1280132	0	40020	40090	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20048	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	15	0	0	10023	16	2	2	11	16	4	2	2	21	21	40036	15	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	16	6	2	9	16	2	2	1	15	20	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	46	99	160010	10	160000	10	160000	50	1280000	0	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	2	3	0	0	10023	16	5	1	20	16	2	2	2	21	9	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	16	5	1	20	16	2	1	2	20	9	40036	30	10	160000	10	40040	40043	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160140	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	13	6	2	20	16	2	1	2	18	8	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	16	5	1	20	16	4	2	1	21	21	40036	30	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	9	46	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	13	5	2	8	16	2	1	1	8	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	80	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	13	5	1	20	16	2	1	1	9	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	10025	13	5	1	20	16	2	1	1	9	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	88	25	160010	10	160000	10	160000	50	1280000	1	1	10	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	13	5	1	20	16	2	1	1	9	20	40036	15	5	160000	10	40040	40040	40040	40040	40040

SQRSHRUN2 (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations