Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRSHRUN (H)

Test 1: uops

Code:

  sqrshrun b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722082254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030843037111001100000073116112701100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqrshrun b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500009004092954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000030071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
10204300372250000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500002400612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500002700612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038
102043003722500003000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500042061295472510018121000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064034162229629010000103003830038300383003830038
100243003722500042061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830038300383003830038
100243003722500045061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830038300383003830038
100243003722500036061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064034242229629010000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830038300383003830038
100243003722500057061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830038300383003830038
100243003722500024061295112510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830038300383003830038
100243003722500051061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000264032162229629010000103003830038300383003830038
100243003722400072061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300371110021109101010000100000064032162229629010000103003830133300383003830038
10024300372250006061295472510010101000010100005042771601330018300373003728286328767100102010000201000030037300375110021109101010000100000064032162229629010000103008630038300383003830038

Test 3: throughput

Count: 8

Code:

  sqrshrun b0, h8, #3
  sqrshrun b1, h8, #3
  sqrshrun b2, h8, #3
  sqrshrun b3, h8, #3
  sqrshrun b4, h8, #3
  sqrshrun b5, h8, #3
  sqrshrun b6, h8, #3
  sqrshrun b7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915001203025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181162120036800001002004020040200402004020040
802042003915030053258010810080008100800205006410400200202003920039997769990801202008003220080032200392003911802011009910010080000100001211151181161120036800001002004020040200402004020040
802042003915000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100002411151181161120036800001002004020040200402004020040
802042003915000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100236311151181161120036800001002004020040200402004020040
802042003915000020125801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010001311151181161120036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000911151181161120036800001002004020040200402004020040
802042003915019883025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000911151181161120036800001002004020040200402004020040
802042003915000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100006611151181161120036800001002004020040200402004020040
802042003915000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100045011151181161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500632580010108000010800005064000020020201432003999963100198001020800002080000200392003911800211091010800001005020716862003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716672003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716792003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020616972003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716962003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716872003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020616992003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716892003680000102004020040200402004020040
80024200391500402580010108000010800005064000020021200392003999963100198001020800002080000200392003911800211091010800001005020616992003680000102004020040200402004020040
80024200391503402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001005020716762003680000102004020040200402004020040