Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHLU (scalar, H)

Test 1: uops

Code:

  sqshlu h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500103168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371500124168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
1004203716013261168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073216211786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371500103168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshlu h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150084196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500145196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007121161119791100001002003820038200382003820038
102042003715018661196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182008420037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037149061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640316221978610000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100003640216221978610000102003820038200382003820038
10024200371501008814919675251001010100001210000502847521120022200372003718443318767100102010000201000020037200841110021109101010000104220640216221978610000102003820038200382003820038
1002420037150000053619686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100003640216221978610000102003820038200742003820038
1002420037150000010319686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100003640216221978610000102003820038200382003820038
1002420037150000010319686251001010100001310000502847521120018200372003718443318767100102010000201016820084200371110021109101010000100103640216221978610000102003820038201332003820038
1002420037150000010319686251001010100001010000502847521120018201322003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640216321978610000102003820038200382003820038
100242003715000306119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshlu h0, h8, #3
  sqshlu h1, h8, #3
  sqshlu h2, h8, #3
  sqshlu h3, h8, #3
  sqshlu h4, h8, #3
  sqshlu h5, h8, #3
  sqshlu h6, h8, #3
  sqshlu h7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150111390029258010810080008100800205006401322001920038200389977699898012020080032200800322003820091118020110099100100800001000011151240616113200350800001002003920039200392003920039
802042003815011000340258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151247116113200350800001002003920039200392003920039
802042003815011000340258010810080008100800205006401322001920038200389977699898012020080032200800322008720038118020110099100100800001000011151247116113200350800001002003920039200392003920039
8020420038150110210340258010810080008100800205006401322001920038200389977699898012020080134200800322003820038118020110099100100800001000011151247116113200350800001002003920039200392009420039
8020420038150110150340258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001002011151247116113200350800001002003920039200392003920039
80204200381501101203402580108100800081008002050064013220019200382003899776100148012020080032200801342003820038118020110099100100800001000011151247116113200350800001002003920039200392003920039
8020420038150110240340258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151247116113200350800001002003920039200392003920039
802042003815011000340258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151247116113200350800001002003920039200392003920039
802042003815011000382258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001001311151247116113200350800001002003920039200392003920039
8020420038150110003272258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151247116113200350800001002003920092200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500000003925800101080000108000050640000020019200382003899960310018800102080000208000020038200381180021109101080000100000050348161714200350080000102003920039200392003920039
8002420038150000000319258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503614161714200350080000102003920039200392003920039
80024200381500000880602580010108000010800005064000002001920038200389996031001880010208000020800002003820038118002110910108000010000005036101610172003515080000102003920039200392003920039
8002420038150000000104258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503416161317200350080000102003920039200392003920039
8002420038150000000165258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503410161710200350080000102003920039200392003920039
800242003815000000039258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000502817161417200350080000102003920039200392003920039
800242003815000000039258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503717161717200350080000102003920039200392003920039
8002420038150000000211258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503410161714200350080000102003920039200392003920039
80024200381500000003925800101080000108000050640000020019200382003899960310018800102080000208000020038200381180021109101080000100000050368161714200350080000102003920039200392003920039
800242003815000000039258001010800001080000506400000200192003820038999603100188001020800002080000200382003811800211091010800001000000503617161717200350080000102003920039200392003920039