Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHLU (vector, 2S)

Test 1: uops

Code:

  sqshlu v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100001073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037160061168625100010001000264521120542037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371501261168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371501261168625100010001000264521120182037203715713189510001000100020372085111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150661168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshlu v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251015110010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100237101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100207101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100107101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715010000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006403162219786010000102003820038200382003820038
1002420037150000000120611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000030611968625100101010000101000050284752112001820037200371844331878810468201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715001000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000001350611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000390611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshlu v0.2s, v8.2s, #3
  sqshlu v1.2s, v8.2s, #3
  sqshlu v2.2s, v8.2s, #3
  sqshlu v3.2s, v8.2s, #3
  sqshlu v4.2s, v8.2s, #3
  sqshlu v5.2s, v8.2s, #3
  sqshlu v6.2s, v8.2s, #3
  sqshlu v7.2s, v8.2s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f203f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000100111511801620035800001002003920039200392003920039
8020420038150000000002943802081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039
8020420038150000000002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000305020316362003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020216232003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120100200392003899963100188001020800002080000200382003811800211091010800001000005020316352003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020216322003580000102003920039200392003920039
8002420038150013925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020316322003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000605020516552003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020316652003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020216232003580000102003920039200392003920039
80024200381500013425800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020316322003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001020005020516332003580000102003920039200392003920039