Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHLU (vector, 4H)

Test 1: uops

Code:

  sqshlu v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160000006116862510001000100026452102018203720371571318951000100010002037203711100110000003073216111786100020382038203820382038
10042037150000006116862510001000100026452112018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
10042037150000006116862510001000100026452102018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
100420371500000010316862510001000100026452102018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
10042037160000006116862510001000100026452112018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
10042037160000006116862510001000100026452112018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
10042037150000006116862510001000100026452102018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
10042037150000006116862510001000100026452112018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
100420371500000013716862510001000100026452102018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038
100420371500001206116862510001000100026452112018203720371571318951000100010002037203711100110000000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshlu v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000120061196862510100100100001001000062828475210200182003720037184213187451042820010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500006061196752510100100100001001000050028475211200182003720037184243187451026220810000200100002003720037211020110099100100100001004000000071011611197910100001002003820038200382003820038
10204200371500003061196862510100100100001001015250028475211200182003720037184243187451010020410000212100002003720037111020110099100100100001000000100071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475211200182003720037184213187451058120010000202100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000003071011611197910100001002003820038200382003820038
102042003715000012061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000396061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000003071011611197910100001002003820038200382003820038
10204200371490009061196862510100100100001001000051728475211200182003720037184213187611010020010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820086

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000001471968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100221010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000821968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037149000000001451968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshlu v0.4h, v8.4h, #3
  sqshlu v1.4h, v8.4h, #3
  sqshlu v2.4h, v8.4h, #3
  sqshlu v3.4h, v8.4h, #3
  sqshlu v4.4h, v8.4h, #3
  sqshlu v5.4h, v8.4h, #3
  sqshlu v6.4h, v8.4h, #3
  sqshlu v7.4h, v8.4h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500008703425801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151184160020035800001002003920039200392003920039
80204200381500002102925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392011020039
80204200381500002402925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000100011151180160020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038201971180201100991001008000010000000011151180160020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392003920039
80204200381500000059925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180161020035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150693925800101080000108000050640000120019200382003899963100188001020800002080000200382013811800211091010800001000502001916992003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020010165112003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050200716482003580000102003920039200392003920039
800242003815029439258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020011169102003580000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000502008161092003580000102003920039200392003920039
80024200381509392580087108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050200916892008580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050200516862003580000102003920039200392003920039
800242003815024392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050200816952003580000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000502009167102003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050200416472003580000102003920039200392003920039