Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHLU (vector, 8B)

Test 1: uops

Code:

  sqshlu v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716010316862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715186116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshlu v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000440071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000030071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000010006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000010604806402162219786010000102003820038200382003820038
100242003715000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000706006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000010006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshlu v0.8b, v8.8b, #3
  sqshlu v1.8b, v8.8b, #3
  sqshlu v2.8b, v8.8b, #3
  sqshlu v3.8b, v8.8b, #3
  sqshlu v4.8b, v8.8b, #3
  sqshlu v5.8b, v8.8b, #3
  sqshlu v6.8b, v8.8b, #3
  sqshlu v7.8b, v8.8b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061150002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100009011151182162120035800001002003920039200392003920039
8020420038150012292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000011151182162120035800001002003920039200392003920039
802042003815010292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000011151182162120035800001002003920039200392003920039
802042003815000502580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000011151182162120035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000015911151182162220035800001002003920039200392003920039
802042003815000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000011151182162220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100008711151182162220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100009011151182162120035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100016011151181162120035800001002003920039200392003920039
802042003815000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010001011151182162120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010050050208161352003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000050206164132003580000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010003005020416352003580000102003920039200392003920039
80024200381490000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000502061612112003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000502011161152003580000102003920039200392003920039
8002420038150000000022925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020716642003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020416662003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020416452003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020216462003580000102003920039200392003920039
800242003815000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020916562003580000102003920039200392003920039