Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHL (immediate, scalar, D)

Test 1: uops

Code:

  sqshl d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020852038203820382038
100420371600611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645211201820372037157131914100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000000073216221786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001163203720371110011000000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshl d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002849735120018200372003718421318745101002001000020010000200372003711102011009910010010000100001000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000044119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371490000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000006119686251001010100001010000502852577120018200372003718443318767100102010000201000020037200371110021109101010000100040006404168319786010000102003820038200382003820038
1002420037150000008219686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006403164319786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006404166419786010000102003820038200382003820038
10024200371500003063119686251001010100481010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006404163419786010000102003820038200382003820038
1002420037150000006119686831001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006404163419786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100010306403163419786010000102003820038200382003820038
10024200371500000010319686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000906403164419786010000102003820038200382003820038
1002420037150000006119686251001010100001010000602847521020018200372003718443318767100102010000201000020037200371110021109101010000100010006404164319786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100010306403163419786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000306404164319786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshl d0, d8, #3
  sqshl d1, d8, #3
  sqshl d2, d8, #3
  sqshl d3, d8, #3
  sqshl d4, d8, #3
  sqshl d5, d8, #3
  sqshl d6, d8, #3
  sqshl d7, d8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915010029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184164020035800001002003920039200392003920039
802042003815000929258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151200160020035800001002003920039200392003920039
8020420038150000280258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500001464258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001001011151184160020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151180160020035800001002003920039200392003920039
8020420038150000124258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815010029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000000852580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000905020616562003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020316352003580000102003920039200392003920039
80024200381500010000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000605020516352003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020516532003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020516532003580000102003920039200392003920039
800242003814900000002292580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000020005020416552003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020316532003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996081001880010208000020800002003820038118002110910108000010000000005020316452003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020516532003580000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000010005020516352003580000102003920039200392003920039