Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHL (immediate, vector, 4H)

Test 1: uops

Code:

  sqshl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000373116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100001373116111786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371502461168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371501861168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000100071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011621197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021611197910100001002003820038200382003820038
10204200371500012006119686251010010410012100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000202292003711102011009910010010000100000107943071011611199330100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000120071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011613197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006405165419822010000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404165519786010000102003820038200382003820038
100242003715010611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404164519786010000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404165419786010000102003820038200382003820038
100242003715010611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404164519786010000102003820038200382003820038
100242003714900611968625100101010000101000050284752112001820037200371845931876710010201000020100002003720037111002110910101000010006404165419786010000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404164519786010000102003820038200382003820038
100242003714900611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006404164519786010000102003820038200382003820038
100242003715010611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006405165519786010000102003820038200382003820038
1002420037150003461968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010036404165519786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sqshl v0.4h, v8.4h, #3
  sqshl v1.4h, v8.4h, #3
  sqshl v2.4h, v8.4h, #3
  sqshl v3.4h, v8.4h, #3
  sqshl v4.4h, v8.4h, #3
  sqshl v5.4h, v8.4h, #3
  sqshl v6.4h, v8.4h, #3
  sqshl v7.4h, v8.4h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
8020420038150309292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
8020420038150402292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181620035800001002003920039200392003920039
802042003815018292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000311151181620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150000000000229258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000050206167720035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000050205165620035080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012017120038200381000431001880010208000020800002003820038118002110910108000010000000050206166720035080000102010920191200392003920039
8002420038150000000000210258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000003050206168820035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000050205165620035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000050207165620035080000102003920039200392003920088
800242003815000000000081258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000050206167520035080000102003920039201882003920039
8002420038150000000000230258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000050206166520035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000050208167520035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000100050206168720035080000102003920039200392003920039