Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHL (scalar, H)

Test 1: uops

Code:

  sqshl h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371501031687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002659631201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371502191687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshl h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000012061196872510100100100001001000050028476800200182008520037184253187631010020410334200206642008520037111020110099100100100001000071011601119791100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038
102042003715000027061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038
102042003715000027061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011601119791100001002003820038200382003820038
102042003715000000612196872510100100100001001000050028476800200182003720037184223187631010020210000200200002003720037211020110099100100100001009071011601119825100001002003820038200382003820038
1020420037150000120103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119826100001002003820038200382003820038
102042003715000000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038
102042003715000012061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038
102042003715010000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011601119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003714931261196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221985310000102003820038200382003820038
1002420037150258611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010012640216221978510000102003820038200382003820038
10024200371500251196872510010101000010100005028476800200182003720037184443187671001020100002020000200372008411100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020360200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715039361196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500726196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500103196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sqshl h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371501806119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001003007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100101505002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715058206119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150606119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371504206119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715046206119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715032706119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000003900611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006403162219785010000102003820038200382003820038
100242003715000002100611968725100101010000101000050284768012001820037200371844431876710010201000020200002008520037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200842008518444318786101622010998202232420274203109110021109101010000100000010958407813983420037110000102032320275203582032120276
1002420320151015666952812986196321361008418100721411064612855378120234203222035518461291887110927221098922219822027620322811002110910101000010200148045007013652219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sqshl h0, h8, h9
  sqshl h1, h8, h9
  sqshl h2, h8, h9
  sqshl h3, h8, h9
  sqshl h4, h8, h9
  sqshl h5, h8, h9
  sqshl h6, h8, h9
  sqshl h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511021611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000124800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000003040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000012040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd2d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000009005020051600065200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000112001920038200389996031001880010208000020160000200382003811800211091010800001000000005020051600065200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000000005020061600055200350080000102003920039200392003920039
8002420038150000001203925800101080000108000050640000012001920038200389996031001880010208000020160000200382003811800211091010800001000000005020051600055200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000000005020071600055200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000102001920038200389996031001880010208000020160000200382003811800211091010800001000000005020051600055200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000000005020081600045200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000112001920038200389996031001880010208000020160000200382003811800211091010800001000000005020071600067200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000000005020041600055200350080000102003920039200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996031001880010208000020160000200382003811800211091010800001000000005020051600065200350080000102003920039200392003920039