Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHL (scalar, S)

Test 1: uops

Code:

  sqshl s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073216111787100020382038203820382038
100420371500082168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000611687251000100010002646800201820372037157231895100010002000203720371110011000002773116111787100020382038203820382038
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371500061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000128168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshl s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000001506119687251010010010000100100005002847680200182003720037184223187451010020010000200200002008420037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000002706119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10205200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000009071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000002661968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116121219785010000102003820038200382003820038
100242003715000000000026619687251001010100001010000502847680120018200372003718444031876710010201000020200002003720037111002110910101000010000000630006441116111119785010000102003820038200382003820038
100242003715000000002402661968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116121219785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116111119785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116111119785010000102003820038200382003820038
100242003715000000000026619687251001010100001010000502847680020018200372003718444031876710010201000020200002003720084111002110910101000010000000960006441116111119785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441216111119785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000013500064411169919785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116111119785010000102003820038200382003820038
10024200371500000000002661968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000000006441116111119785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sqshl s0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000000028819687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100002700071021622197910100001002003820038200382003820038
102042003714900000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003714900000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000086219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100002800071021622197910100001002003820038200382003820038
102042003715000010000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
1020420037150000000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002600071021622197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000900640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100004780640216221978510000102003820038200382003820038
100242003715001000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000030640216221978510000102003820038200382003820038
100242003715010010821967625100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000030640216221978510000102008620086200382003820086
100242003715001101715361968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010220200640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000100640216221982310000102003820179200382003820038
100242003715001000821968761100101010012101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003714900000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sqshl s0, s8, s9
  sqshl s1, s8, s9
  sqshl s2, s8, s9
  sqshl s3, s8, s9
  sqshl s4, s8, s9
  sqshl s5, s8, s9
  sqshl s6, s8, s9
  sqshl s7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381500000000822580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511031611200350800001002003920039200392003920063
80204200381500000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
802042003815000000001262580100100800001008000050064000002001920038200389973399968010020080000200160000200382008821802011009910010080000100000000511011611200350800001002008820039200392003920039
802042003815000100001172580197121800001018009650064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200850800001002003920039200392003920144
80204200971500000000404680100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500000000942580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
802042003815000000001244680211100800001058009650064000002006320089200389973399968010020080000200160000200382003811802011009910010080000100000104512711611200350800001002003920039200392003920039
80204200381500000000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
802042003815000001200822580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500000000612580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150000014425800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050204160242003500080000102003920039200392003920039
80024200381500000229258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100300350204160242003500080000102003920039200392003920039
800242003815000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050202160422003500080000102003920039200392003920039
8002420038150000010425800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050204160422003500080000102003920039200392003920039
80024200381500000101525800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050204160242003500080000102003920039200392003920039
80024200381500000441258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100160050202160422003500080000102003920039200392003920039
8002420038150000019925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050204160422003500080000102003920039200392003920039
800242003815000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050204160422003500080000102003920039200392003920039
800242003815000003925800101080000108000050640000112001920038200389996310018800102080000201600002003820038118002110910108000010000050204160422003500080000102003920039200392003920039
800242003815000008325800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050202160442003500080000102003920039200392003920039