Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHL (vector, 8B)

Test 1: uops

Code:

  sqshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160821687251000100010002646802018203720371572318951000100020002037203711100110000973116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037166611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371503341687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sqshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000156061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071021611197910100001002003820038200382003820085
10204200371500000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000943196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197912100001002003820038200382003820038
1020420037150000384061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000321061196872510100100100001001000050028476802001820037200371842203187451058820010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500002880536196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000264061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000378009719687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006403162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000606402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000024006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000004290053619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003714900000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500000441008919687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500000336006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sqshl v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000600611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003714900000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820083
102042003715000000000821968725101001001000010010000500284768012001820037200371842231874510100208100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000002400611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000002700611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000300611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820085200382003820038
102042003715000000000821968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000002400611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371501206119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371506061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001038600640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371502106119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371503606119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371502706119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000101000640216221978510000102003820038200382003820038
10024200371500075419687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sqshl v0.8b, v8.8b, v9.8b
  sqshl v1.8b, v8.8b, v9.8b
  sqshl v2.8b, v8.8b, v9.8b
  sqshl v3.8b, v8.8b, v9.8b
  sqshl v4.8b, v8.8b, v9.8b
  sqshl v5.8b, v8.8b, v9.8b
  sqshl v6.8b, v8.8b, v9.8b
  sqshl v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500000004025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000027051105121611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000081051105111611200350800001002003920039200392003920039
80204200381500000009725801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000030051105111611200350800001002003920039200392003920039
80204200381500000005025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000030051105111611200350800001002003920039200392003920039
80204200891500000004025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100020012051105111611200350800001002003920039200392008720039
80204200381500000004025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000027051105111611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051105111611200350800001002003920039200392003920039
802042003815000003304025801001008000010080000500640000152001920038200389973399968010020080000200160000200382003811802011009910010080000100000021051105111611200350800001002003920039200392003920039
8020420038150000000402580100100800001008000050064000015200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051105111611200350800001002003920039200392003920039
8020420038150000000502580100100800001008000050064308815200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051105111611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150110246258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100300502400171616152003580000102003920039200392003920039
8002420038150110246258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502400181616162003580000102003920039200392003920039
8002420038150111224625800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050240315161682003580000102003920039200392003920039
80024200381501129124625800101080000108000050640000102001920038200389996310018800102080000201600002003820038318002110910108000010230050240018161472003580000102003920039200392003920039
8002420038150110246258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502400171611172003580000102003920039200392003920039
8002420038150110246258001010800001080000506400000320019200382003899963100188001020800002016000020038200381180021109101080000100000502400161616162003580000102003920039200392003920039
8002420038150110246258001010800001080000506400000320019200382003899963100188001020800002016000020038200381180021109101080000100000502400161616162003580000102003920039200392003920039
80024200381501121246258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100000502400161616162003580000102003920039200392003920039
800242003815011452462580010108000010800005064000003200192003820038999631001880010208000020160000200382003811800211091010800001000005024009169152003580000102003920039200392003920039
8002420038150110246258001010800001080000506400000320019200382003899963100188001020800002016000020038200381180021109101080000100000502400161614142003580000102003920039200392003920039