Firestorm: SQSHRN2 (4S) measurements

Code:

  sqshrn2 v0.8h, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	7	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	12	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	12	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sqshrn2 v0.8h, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	175	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	145	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30085	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	210	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10025	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	166	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	3	2	29630	0	10000	10	30086	30168	30038	30038	30038
10024	30133	225	1	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30084	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	212	29548	45	10019	10	10000	10	10149	60	4277313	1	30018	30037	30037	28290	8	28767	10010	20	10329	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	12	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sqshrn2 v0.8h, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	30034	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	224	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	202	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	995	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	6	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	145	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqshrn2 v0.8h, v8.4s, #3
  movi v1.16b, 0
  sqshrn2 v1.8h, v8.4s, #3
  movi v2.16b, 0
  sqshrn2 v2.8h, v8.4s, #3
  movi v3.16b, 0
  sqshrn2 v3.8h, v8.4s, #3
  movi v4.16b, 0
  sqshrn2 v4.8h, v8.4s, #3
  movi v5.16b, 0
  sqshrn2 v5.8h, v8.4s, #3
  movi v6.16b, 0
  sqshrn2 v6.8h, v8.4s, #3
  movi v7.16b, 0
  sqshrn2 v7.8h, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	151	15	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	90	124	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10120	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	93	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	84	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	75	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10120	1	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	426	504	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10120	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	102	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	493	1	1	1	10120	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	90	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	99	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	1	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20086	150	0	0	1	0	0	51	66	80010	10	80000	10	80000	50	640000	1	1	5	20029	20050	20046	3	22	80114	20	80000	20	160210	20052	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10044	13	3	2	24	144	3	1	1	15	18	20049	30	160000	10	20047	20047	20053	20053	20047
160024	20048	150	0	0	0	9	264	51	64	80010	10	80000	10	80000	50	640832	0	1	10	20031	20050	20050	3	22	80010	20	80000	20	160000	20062	20046	1	1	160021	10	9	10	10	160000	10	0	2	0	0	0	10042	13	5	1	19	173	4	2	2	19	22	20049	30	160000	10	20051	20053	20053	20053	20051
160024	20050	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	0	1	10	20033	20050	20050	3	22	80010	20	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10044	13	5	1	21	179	4	1	2	19	20	20049	15	160000	10	20047	20051	20049	20053	20051
160024	20052	150	0	0	0	0	0	45	25	80010	10	80104	10	80000	50	640000	1	1	10	20027	20046	20048	3	22	80010	20	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10042	13	5	1	20	163	2	1	1	17	18	20043	15	160000	10	20049	20047	20047	20049	20049
160024	20048	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20029	20046	20048	3	22	80010	20	80000	20	160000	20052	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10042	13	5	1	19	141	2	1	1	19	18	20043	15	160000	10	20047	20047	20049	20049	20049
160024	20048	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20048	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10036	13	5	1	18	139	2	1	1	20	20	20045	15	160000	10	20049	20049	20049	20047	20049
160024	20046	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20052	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10040	13	5	1	18	139	2	1	1	16	18	20043	16	160000	10	20049	20047	20047	20049	20047
160024	20048	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10043	13	5	1	18	147	2	1	1	19	18	20045	15	160000	10	20047	20047	20047	20047	20049
160024	20046	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20029	20046	20046	3	22	80010	20	80000	20	160000	20053	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10041	13	5	1	19	142	2	1	1	18	17	20043	16	160000	10	20047	20047	20047	20047	20049
160024	20046	150	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	10	20027	20046	20046	3	22	80010	20	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10041	13	5	1	13	136	2	1	1	13	15	20047	15	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  sqshrn2 v0.8h, v16.4s, #3
  sqshrn2 v1.8h, v16.4s, #3
  sqshrn2 v2.8h, v16.4s, #3
  sqshrn2 v3.8h, v16.4s, #3
  sqshrn2 v4.8h, v16.4s, #3
  sqshrn2 v5.8h, v16.4s, #3
  sqshrn2 v6.8h, v16.4s, #3
  sqshrn2 v7.8h, v16.4s, #3
  sqshrn2 v8.8h, v16.4s, #3
  sqshrn2 v9.8h, v16.4s, #3
  sqshrn2 v10.8h, v16.4s, #3
  sqshrn2 v11.8h, v16.4s, #3
  sqshrn2 v12.8h, v16.4s, #3
  sqshrn2 v13.8h, v16.4s, #3
  sqshrn2 v14.8h, v16.4s, #3
  sqshrn2 v15.8h, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	24	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	51	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40090	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	2	3	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	695	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40021	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	3	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	36	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	6	4	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	51	67	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	7	16	2	1	1	4	5	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	711	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	6	16	2	1	1	3	5	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	10022	3	1	1	7	16	2	1	1	5	5	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	9	16	2	1	1	5	5	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	7	16	2	1	1	5	3	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	6	2	2	7	16	4	2	2	6	8	40036	40	12	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	7	7	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	6	4	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	7	4	40036	20	6	160000	10	40040	40040	40040	40040	40040

SQSHRN2 (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations