Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHRN2 (8H)

Test 1: uops

Code:

  sqshrn2 v0.16b, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300145254825100010001000398313030183037303724153289510001000200030373037111001100000073116112702100030383038303830383038
1004303722132061254825100010001000399230130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372212061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372212061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030863038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722132061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  sqshrn2 v0.16b, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000017101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295392510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000010006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000020006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000020006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018300373003728287732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000103230421659327912724229884310000103036830367303693032330272
1002430367228000779366164592294761611007115100641410894604286812030270303693012028313030289171091022111492022300304173036611100211091010100001062013541935126402242229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  sqshrn2 v0.16b, v0.8h, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030918191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000009011171716296450100001003003830038300383003830038
1020430037224000061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000000011171816296450100001003023030038300383003830038
10204300372250000726295472510131100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000000411171816296450100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000000011171816296460100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000000011171716296460100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000000011171816296450100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000000011171716296450100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282717287411025420010008200200163003730037111020110099100100100001000122808011171716296450100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000000011171816296450100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282717287411010020010008200200163003730037111020110099100100100001000000011171816296450100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000005362954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100010640224322962910000103003830038300383027230086
100243003722501000612954725100101010000101000050427716030018300373003728286328767101622010000202033630084300371110021109101010000102110640216222962910000103003830038300383003830038
1002430037224000007262954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427787930018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300853008630038
100243003722500000612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500000612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722400000612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000009242954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqshrn2 v0.16b, v8.8h, #3
  movi v1.16b, 0
  sqshrn2 v1.16b, v8.8h, #3
  movi v2.16b, 0
  sqshrn2 v2.16b, v8.8h, #3
  movi v3.16b, 0
  sqshrn2 v3.16b, v8.8h, #3
  movi v4.16b, 0
  sqshrn2 v4.16b, v8.8h, #3
  movi v5.16b, 0
  sqshrn2 v5.16b, v8.8h, #3
  movi v6.16b, 0
  sqshrn2 v6.16b, v8.8h, #3
  movi v7.16b, 0
  sqshrn2 v7.16b, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009115000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066200662006620066
1602042006515000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002013220066200662006620066
1602042006515000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066200662006620066
16020420065150000409258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066200662006620066
1602042006515010029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066201342006620066
1602042006515000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066200662006620066
1602042006515100029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011917200621600001002006620066200662006620066
1602042006515000504292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000541111011916200621600001002006620066200662006620066
1602042006515000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100031111011916200621600001002006620066200662006620066
1602042006515000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100001111011916200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242009015045278001010800001080000506400001102003220051200513228001020800002016000020051200511116002110910101600001000100273214252113420048202160000102005220052200522005220052
1600242005115045278001010800001080000506400001152003220051200513228001020800002016000020051200511116002110910101600001010100278413252114420048201160000102005220052200522005220052
1600242005115045278001010800001080000506400001002003220051200513228001020800002016000020051200511116002110910101600001010100278524252114520048201160000102005220052200522005220372
16002420051150546278001010800001080000506400001002003220051200513228001020800002016000020051200511116002110910101600001000100278414252114320048201160000102005220052200522005220052
1600242005115045278001010800001080000506400001152003220051200513228001020800002016000020051200511116002110910101600001000100278413252113420048401160000102005220052200522005220052
1600242005115145278001010800001080000506400001052003220051200513228001020800002016000020051200511116002110910101600001010100268114252114420048201160000102005220052200522005220052
1600242005115045278001010800001080000506400001152003220051200513228001020800002016000020051200511116002110910101600001000100278414252114420048201160000102005220052200522005220052
1600242005115045278001010800001080000506400001152003220051200513228001020800002016000020051200511116002110910101600001000100278415252114320048201160000102005220134200522005220052
1600242005115045278001010800001080000506400001152003220051200513518001020800002016000020051200511116002110910101600001000100288415252113420048201160000102005220052200522005220052
1600242005115045278001010800001080000506400001152003220051200513228001020800002016000020051200511116002110910101600001000100278413252113420048201160000102005220052200522005220052

Test 5: throughput

Count: 16

Code:

  sqshrn2 v0.16b, v16.8h, #3
  sqshrn2 v1.16b, v16.8h, #3
  sqshrn2 v2.16b, v16.8h, #3
  sqshrn2 v3.16b, v16.8h, #3
  sqshrn2 v4.16b, v16.8h, #3
  sqshrn2 v5.16b, v16.8h, #3
  sqshrn2 v6.16b, v16.8h, #3
  sqshrn2 v7.16b, v16.8h, #3
  sqshrn2 v8.16b, v16.8h, #3
  sqshrn2 v9.16b, v16.8h, #3
  sqshrn2 v10.16b, v16.8h, #3
  sqshrn2 v11.16b, v16.8h, #3
  sqshrn2 v12.16b, v16.8h, #3
  sqshrn2 v13.16b, v16.8h, #3
  sqshrn2 v14.16b, v16.8h, #3
  sqshrn2 v15.16b, v16.8h, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440061300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081689400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118071687400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081687400361600001004004040040400404004040040
16020440039299000003025160108100160008100160020500128013214002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081678400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081688400361600001004004040040400404004040040
16020440039300000005825160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081688400361600001004004040040400404004040040
16020440039299000003025160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081788400361600001004004040040400404004040040
16020440039299000003025160108100160008100160020500128013204002040039400391997762002416012020016003220032006440039400391116020110099100100160000100000011110118081688400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118081638400361600001004004040040400404004040040
16020440039300000003025160108100160008100160020500128013204002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000011110118071688400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440050300000000046251600101016000010160000501280000110400204003940039199960320019160010201600002032000040039400391116002110910101600001000000100223110221621121194003621118160000104004040040400904004040040
1600244003930000000004625160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022841019162111317400362081160000104004040040400404004040040
1600244003930000000004625160010101600001016000050128000010540020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022841120161111820400362167160000104004040040400404004040040
160024400393000000000711251600101016000010160000501280000105400204003940039199960320019160010201600002032000040039400391116002110910101600001000000100221141019161112115400362154160000104004040040400404004040040
1600244003930000000004625160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022811014161211617400362054160000104004040040400404004040040
1600244003930000000004625160010101600801016000050128000001040020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022341020161111713400362065160000104004040040400404004040040
1600244003930000000004625160010101600001016000050128000010040020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022811018162211718400364077160000104004040040400404004040040
1600244003930000000006725160010101600001016000050128000011040020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022841018163111919400364077160000104004040040400404004040040
16002440039299000000052125160010101600001016000050128000010540020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022811017162111420400364055160000104004040040400404004040040
16002440039300000039004625160010101600001016000050128000011540020400394003919996032001916001020160000203200004003940039111600211091010160000100000010022341017162121819400362054160000104004040040400404004040040