Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHRN (2D)

Test 1: uops

Code:

  sqshrn v0.2s, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372301242547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037220612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981601305430373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037239612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073116112706100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  sqshrn v0.2s, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501320744295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100200071011611296330100001003003830038300383003830038
102043003722400061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771600300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037225012061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037225039061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000371011611296330100001003003830038300383003830038
10204300372250270612954725101001001001613210000500427851213001830037300372826403287451010020010000200100003003730037111020110099100100100001000010710116112963314100001003003830086300863008630038
1020430037225027061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500006306129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722500002406129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160300183300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722500002706129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722500003006129547251001010100001010000504277160300180300373003728286328767100102010339201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722500002406129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722400001206129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000006403163329629010000103003830038300383003830038
100243003722500003906129547251001010100001010000504277160300180300373003728286328767100102010000201000030037300371110021109101010000100000007675738529904410000103027430320303713036930367
10024301212281172948616513629484821006815100561510900504277160300180300373003728286328767100102010000201000030037300372110021109101010000100100006403163329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sqshrn v0.2s, v8.2d, #3
  sqshrn v1.2s, v8.2d, #3
  sqshrn v2.2s, v8.2d, #3
  sqshrn v3.2s, v8.2d, #3
  sqshrn v4.2s, v8.2d, #3
  sqshrn v5.2s, v8.2d, #3
  sqshrn v6.2s, v8.2d, #3
  sqshrn v7.2s, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581511010002730258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
802042003915010100003025801081008000810080020500640132200200200392003999776999080120200800322008003220039200391180201100991001008000010000470011151181161120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151361161120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
80204200391501010001230258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161120036800001002004020040200402004020040
80204200391501010003030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100000011151181261120036800001002004020040200402004020040
8020420039150101000030258010810080008100800205006401322002002003920039997769990801202008003220080032200392003911802011009910010080000100040011151182161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511506040258001010800001080000506400000200202003920039999631001980010208000020800002003920039218002110910108000010050207160642003680000102004020040200402004020040
8002420039150147063258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050204160462003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200692003920039999631001980010208000020800002003920039118002110910108000010050207160652003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050206160462003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010050206160642003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050204160462003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010050206160562003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050206160642003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050205160462003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010050204160642003680000102004020040200402004020040