Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
sqshrn v0.2s, v0.2d, #3
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 1004 | 3037 | 23 | 0 | 124 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 22 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 1 | 3054 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 1 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 9 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2706 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 1 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
| 1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
Code:
sqshrn v0.2s, v0.2d, #3
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
| retire uop (01) | cycle (02) | 03 | 18 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 30037 | 225 | 0 | 132 | 0 | 744 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 2 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 224 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 12 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 39 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 3 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10204 | 30037 | 225 | 0 | 27 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10016 | 132 | 10000 | 500 | 4278512 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 1 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 14 | 10000 | 100 | 30038 | 30086 | 30086 | 30086 | 30038 |
| 10204 | 30037 | 225 | 0 | 27 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 0 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | c2 | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 63 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 24 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 3 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 27 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 30 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10339 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 24 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 224 | 0 | 0 | 0 | 0 | 12 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
| 10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 39 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 767 | 5 | 73 | 8 | 5 | 29904 | 4 | 10000 | 10 | 30274 | 30320 | 30371 | 30369 | 30367 |
| 10024 | 30121 | 228 | 1 | 1 | 7 | 2 | 948 | 616 | 5136 | 29484 | 82 | 10068 | 15 | 10056 | 15 | 10900 | 50 | 4277160 | 30018 | 0 | 30037 | 30037 | 28286 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 2 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 1 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Count: 8
Code:
sqshrn v0.2s, v8.2d, #3 sqshrn v1.2s, v8.2d, #3 sqshrn v2.2s, v8.2d, #3 sqshrn v3.2s, v8.2d, #3 sqshrn v4.2s, v8.2d, #3 sqshrn v5.2s, v8.2d, #3 sqshrn v6.2s, v8.2d, #3 sqshrn v7.2s, v8.2d, #3
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | ld unit uop (a6) | l1d cache writeback (a8) | ac | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 20058 | 151 | 1 | 0 | 1 | 0 | 0 | 0 | 27 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 470 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5136 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 12 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 30 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 26 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80204 | 20039 | 150 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 20020 | 0 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 4 | 0 | 0 | 1 | 1 | 1 | 5118 | 2 | 16 | 1 | 1 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | 1e | 3a | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | cf | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 20051 | 150 | 6 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 7 | 16 | 0 | 6 | 4 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 147 | 0 | 63 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 4 | 16 | 0 | 4 | 6 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20069 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 7 | 16 | 0 | 6 | 5 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 6 | 16 | 0 | 4 | 6 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 6 | 16 | 0 | 6 | 4 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 4 | 16 | 0 | 4 | 6 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 6 | 16 | 0 | 5 | 6 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
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| 80024 | 20039 | 150 | 0 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 5020 | 4 | 16 | 0 | 6 | 4 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |